Display Driving Circuit Frame Rate Extraction and Flicker Prevention

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Solution Overview

Problem

Display devices experience image tearing and output distortion due to mismatched frame rates between host processors and display devices, leading to reduced luminance and flicker issues when operating in variable frame rate modes.

Innovation Solution

Incorporating a frame rate extractor and image corrector in display driving circuits to extract frame rates from vertical synchronization signals and perform gamma correction and color correction, thereby synchronizing frame data with the extracted frame rates to reduce delays and prevent flicker.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a variable frame mode is used to match frame rates between host processor and display device, then tearing is reduced, but luminance is reduced and flicker occurs due to increased blank period

Engineering Contradiction:
Improveimage stabilityVSAvoidluminance
Core Design Contradiction:
ReliabilityVSIllumination intensity

Solution Approach 1:

The patent extracts the frame rate from the vertical synchronization signal in advance, before processing the frame data. This preliminary extraction allows the system to prepare appropriate correction parameters ahead of time, enabling timely gamma and color corrections that compensate for luminance reduction during variable frame rate operation, thus preventing flicker while maintaining image stability

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If frame rate extraction is delayed, then processing complexity is reduced, but image quality deteriorates and flicker occurs

Engineering Contradiction:
Improveprocessing complexityVSAvoidimage quality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the processing pipeline into distinct stages: first extracting the frame rate from the vertical synchronization signal, then using this extracted frame rate to guide subsequent gamma correction and color correction processes. This segmentation allows each stage to operate independently and efficiently, maintaining high image quality without excessive processing complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The frame rate extraction is performed in advance before frame data processing begins. This preliminary action provides the necessary timing information upfront, allowing the system to optimize subsequent processing steps without delays that would compromise image quality or cause flicker

Inventive Principle:
Principle #10Preliminary action

3Productivity

If gamma correction and color correction are not performed based on extracted frame rate, then processing time is reduced, but image quality deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoidimage quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent dynamically adjusts gamma correction and color correction parameters based on the extracted frame rate. By changing these parameters according to the actual frame rate conditions, the system maintains high image quality across variable frame rates without requiring excessive processing time, as the corrections are applied efficiently using pre-determined lookup tables or algorithms

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11875761B2Display driving circuit and display device including the same
Publication Date: 2024.01.16 SAMSUNG ELECTRONICS CO LTD
  • US11875761B2 patent drawing
  • US11875761B2 patent drawing
  • US11875761B2 patent drawing

AI summary

A display driving circuit includes a frame rate extractor configured to receive a vertical synchronization signal indicating a start of a k-th frame, k-th frame data including information about the k-th frame, and a data enable signal indicating an active period of the k-th frame and a variable blank period that occurs after the active period, and extract a frame rate of the k-th frame, based on the vertical synchronization signal; and an image corrector configured to correct frame data received after reception of the k-th frame data, based on the frame rate of the k-th frame, and output the corrected frame data as output image data, wherein the vertical synchronization signal is received before a start time point of the active period.