Display Driving Circuit Reduces Bandwidth via Frame Segmentation
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Solution Overview
Problem
Current near-eye display devices for virtual and augmented reality struggle with efficient transmission and rendering of high-resolution images, leading to increased interface bandwidth and buffer memory requirements, which can result in video latency and power consumption issues.
Innovation Solution
A display driving circuit and system that processes and transmits high-resolution images by mixing low-resolution and high-resolution frame data, using a host interface circuit, image processing circuit, and timing controller to up-scale and synthesize frame data, reducing the need for buffer memory and interface bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-resolution frame data is transmitted through a single channel, then interface bandwidth is reduced, but transmission time increases causing video latency
Solution Approach 1:
The patent divides a single high-resolution frame into multiple lower-resolution sub-frames (first frame data and second frame data) and transmits them through multiple parallel signal channels. This segmentation allows the total data to be distributed across channels, reducing the time required for transmission while maintaining the overall high-resolution output when the sub-frames are synthesized.
2Reliability
If buffer memory is used to store frame data, then image quality is maintained, but device complexity and power consumption increase
Solution Approach 1:
The patent employs a bufferless architecture where the image processing circuit directly processes and synthesizes frame data from multiple channels without requiring intermediate buffer memory storage. The system self-manages the timing and synchronization of multiple data streams through coordinated processing, eliminating the need for separate buffer memory components while maintaining image quality.
3Reliability
If buffer memory is used to store frame data, then image quality is maintained, but power consumption increases
Solution Approach 1:
The bufferless image processing architecture eliminates the power consumption associated with buffer memory operations. The system achieves its function through direct processing paths and coordinated timing control, removing the energy-intensive memory read/write operations while maintaining the ability to produce high-quality synthesized output.
4Loss of time
If multiple signal channels are used to transmit frame data, then video latency is reduced, but interface bandwidth requirements increase
Solution Approach 1:
The patent segments high-resolution frame data into multiple lower-resolution sub-frames that can be transmitted simultaneously through multiple signal channels. While this does increase the number of channels required, each channel carries less data, allowing for parallel transmission that reduces overall latency. The segmentation enables a trade-off where channel count increases but individual channel bandwidth requirements decrease.
Data Source
AI summary
A display device including a host interface circuit configured to receive first frame data through a first signal channel and second frame data through a second signal channel, a pixel array including a plurality of pixels, and a plurality of gate lines and a plurality of source lines connected to the plurality of pixels, and an image processing circuit configured to process the first frame data and the second frame data such that the pixel array displays one image including a first area rendered with a first quality and a second area rendered with a second quality that is different from the first quality during one frame period.