Display Driving Circuit Frequency Correction via PWM Signal
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Solution Overview
Problem
Conventional display driving circuits face challenges in quickly correcting frequency changes of the clock signal, especially when operating at low scan rates, leading to image quality degradation due to increased correction time required by longer vertical synchronizing signal periods.
Innovation Solution
A display driving circuit incorporating a frequency correction circuit that utilizes a Pulse Width Modulation (PWM) synchronizing signal with a shorter period than the vertical synchronizing signal to rapidly correct frequency deviations in the oscillator clock signal, allowing for quick stabilization of the frequency even at low scan rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the scan rate is changed to a low scan rate such as 1 Hz or 10 Hz to reduce power consumption, then power consumption is reduced, but the period of the vertical synchronizing signal increases, causing the correction time to increase and image quality to degrade
Solution Approach 1:
The patent segments the synchronizing signal into two types: vertical synchronizing signal (for frame timing) and PWM synchronizing signal (for frequency correction). This segmentation allows the frequency correction function to operate independently with a shorter period signal, resolving the contradiction between low scan rate operation and quick frequency correction capability
Solution Approach 2:
The patent introduces the PWM synchronizing signal as an intermediary element between the oscillator and the frequency correction circuit. This intermediary signal with a fixed short period enables rapid frequency measurement and correction without being constrained by the long period of the vertical synchronizing signal at low scan rates
2Duration of action of moving object
If the period of the vertical synchronizing signal increases to accommodate low scan rates, then the scan rate is reduced for power saving, but the time required for correcting frequency change increases
Solution Approach 1:
The patent divides the synchronizing signal functions into two separate signals: vertical synchronizing signal for frame timing and PWM synchronizing signal for frequency correction. This allows the correction operation to use a short-period signal independent of the frame rate, maintaining high correction speed even when frame period is long
Solution Approach 2:
The patent dynamically selects different synchronizing signals for different functions based on operational requirements. The PWM synchronizing signal with fixed short period is used specifically for frequency correction operations, ensuring that correction speed remains high regardless of the display refresh rate
Data Source
AI summary
Disclosed are a display driving circuit and a frequency correction method of the display driving circuit, capable of quickly correcting a frequency change of a clock signal when a display device is driven at a low scan rate.