Display Panel Driving Circuit Frequency Masking

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Solution Overview

Problem

Existing display devices face challenges in reducing power consumption and minimizing the non-display area, especially when handling multiple images simultaneously.

Innovation Solution

A display panel driving circuit is introduced, which includes a scan driving circuit with multiple scan stages receiving clock signals and a carry signal. The timing controller divides the display panel into different areas and controls the scan driving circuit to operate at varying frequencies, reducing power consumption by masking partial periods of clock signals in certain areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the display panel operates at high frequency to display multiple images, then the display performance is improved, but the power consumption increases

Engineering Contradiction:
Improvedisplay performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by dividing the display panel into different display areas (first display area and second display area) and assigning different operating frequencies to each area. The first display area operates at a first frequency while the second display area operates at a second frequency, allowing regions with different content requirements to be optimized independently for both performance and power consumption.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by enabling the display panel to dynamically adjust operating frequencies based on content requirements. The timing controller can flexibly assign different frequencies to different display areas depending on whether the content is static or dynamic, allowing the system to adapt its power consumption and performance characteristics to match actual display needs.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the scan driving circuit operates continuously to maintain display functionality, then the display reliability is improved, but the power consumption increases

Engineering Contradiction:
Improvedisplay functionalityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by implementing different scan frequencies for different display areas. The first scan frequency is applied to the first display area while a second, lower scan frequency is applied to the second display area. This periodic scanning approach maintains display functionality in all areas while reducing the overall power consumption by not continuously scanning all areas at the same high frequency.

Inventive Principle:
Principle #19Periodic action

3Productivity

If the non-display area is reduced to increase display area, then the display efficiency is improved, but the circuit layout complexity increases

Engineering Contradiction:
Improvedisplay efficiencyVSAvoidcircuit layout
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the scan driving circuit into multiple independent scan stages (first scan stage, second scan stage, etc.), each corresponding to different display areas. This segmentation allows the circuit to be systematically organized and managed, enabling reduced non-display area while maintaining layout manageability through modular design of the scanning architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12211424B2Display panel driving circuit and display device including the same
Publication Date: 2025.01.28 SAMSUNG DISPLAY CO LTD
  • US12211424B2 patent drawing
  • US12211424B2 patent drawing
  • US12211424B2 patent drawing

AI summary

A display panel driving circuit includes a scan driving circuit including a scan stage and a timing controller. The scan stage includes a first circuit connected to a first input node of receiving a first clock signal, a second circuit connected to a second input node of receiving a second clock signal, a third circuit connected to a third input node of receiving a carry signal, the first circuit, and the second circuit and connected to a first control node and a second control node, a pull-up transistor electrically connected to the first input node and an output node of outputting a scan signal and turned on/off by the first control node, and a pull-down transistor electrically connected to the output node and a low-level voltage line and turned on/off by the second control node.