Display Driving Circuit Odd-Even Gate Line Activation
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Solution Overview
Problem
Existing display technologies face challenges in accurately driving gate lines, leading to potential errors in displaying special images, such as interlaced patterns, resulting in lower display quality.
Innovation Solution
A driving circuit comprising a level conversion unit and a gate electrode driving unit, which converts input clock signals into output signals to sequentially shift and output gate scan signals, ensuring accurate row-by-row activation of gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate line driving circuit is used, then the circuit structure is simple, but display errors occur in special images such as interlaced patterns
Solution Approach 1:
The gate signal output is divided into two separate groups: odd-numbered gate signals and even-numbered gate signals. Each group is driven by independent clock signals (first clock signal for odd, second clock signal for even), allowing separate control and preventing display errors in special images while maintaining circuit simplicity
Solution Approach 2:
Different clock signals are applied to different groups of gate lines based on their numbering (odd vs even). This local differentiation in signal timing allows the circuit to handle special image patterns correctly without requiring complete circuit redesign
2Measurement precision
If gate lines are activated simultaneously, then the driving speed is fast, but row-by-row scanning accuracy is lost
Solution Approach 1:
The gate lines are activated in periodic sequences using alternating clock signals. Odd-numbered gate lines are activated during one clock cycle phase, while even-numbered gate lines are activated during the next phase, ensuring precise row-by-row scanning while maintaining continuous operation speed
Data Source
AI summary
A driving circuit, a display device, and a driving method are disclosed. The driving circuit includes a level conversion unit and a gate electrode driving unit; and the gate electrode driving unit is configured to sequentially shift and output a plurality of first gate scan signals by a first portion of the 2n gate signal output terminals in response to a first portion of the plurality of first output signals received at a first moment by a first portion of the plurality of second clock signal input terminals, and sequentially output a plurality of second gate scan signals by a second portion of the 2n gate signal output terminals in response to a second portion of the plurality of first output signals received at a second moment by a second portion of the plurality of second clock signal input terminals.