Display Driving Circuit Jitter Generator for Eye Margin Testing

Solution Overview

Problem

There is a need for an efficient and stable interface circuit that can recover clock and data signals effectively in display devices, particularly in OLED display panels, to improve resolution and reduce bit error rates, which existing technologies have not adequately addressed.

Innovation Solution

A display driving circuit is developed that includes a clock data recovery circuit with a jitter generator, an eye margin test circuit, and a bit error check circuit, which generates a clock signal with adjustable jitter and measures eye margin at high speeds, using a phase locked loop and variable current sources to sample and deserialize data signals, and a digital-analog converter to generate vertical measurement voltages for accurate bit error rate measurement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional eye margin test circuit is used, then the circuit can measure eye margin, but the circuit occupies large area and consumes high power

Engineering Contradiction:

Improveeye margin measurement capabilityVSAvoideye margin test circuit area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent merges the eye margin test circuit with the clock data recovery circuit by sharing common components such as the phase locked loop circuit, sampler, and deserializer. The eye margin test circuit uses the same PLL circuit that recovers clock signals from data signals, eliminating the need for separate dedicated test circuitry and thereby reducing overall circuit area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The phase locked loop circuit and sampler are designed to serve dual purposes: they function as part of the clock data recovery process while simultaneously enabling eye margin measurement. This multi-functionality allows a single circuit to perform both data recovery and measurement tasks, reducing the need for additional dedicated measurement hardware.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Measurement precision

If a conventional eye margin test circuit is used, then the circuit can measure eye margin, but the circuit consumes high power

Engineering Contradiction:

Improveeye margin measurement capabilityVSAvoideye margin test circuit power consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent merges the eye margin test circuit with the clock data recovery circuit by sharing common components such as the phase locked loop circuit, sampler, and deserializer. The eye margin test circuit uses the same PLL circuit that recovers clock signals from data signals, eliminating the need for separate dedicated test circuitry and thereby reducing overall circuit area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The phase locked loop circuit and sampler are designed to serve dual purposes: they function as part of the clock data recovery process while simultaneously enabling eye margin measurement. This multi-functionality allows a single circuit to perform both data recovery and measurement tasks, reducing the need for additional dedicated measurement hardware.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If the eye margin test circuit area is reduced, then the circuit is more compact, but the measurement speed may be compromised

Engineering Contradiction:

Improveeye margin test circuit areaVSAvoideye margin measurement speed

Core Design Contradiction:

Area of stationary objectVSSpeed

Solution Approach 1:

The patent performs preliminary actions by continuously monitoring data signals and maintaining synchronized sampling through the phase locked loop circuit. The sampler is pre-configured to sample data at optimal times determined by the recovered clock signals, enabling rapid eye margin measurement without requiring additional processing time or resources.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The eye margin measurement process continues uninterrupted as the sampler continuously monitors data signals and the phase locked loop maintains continuous synchronization. This continuous operation allows the circuit to perform measurements at high speed without requiring periodic interruptions or additional processing cycles, maintaining measurement speed despite the reduced circuit area.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11996065B2Display driving circuit, display device including the same, and method of operating the same

Publication Date: 2024.05.28 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.