Display Driving Circuit with Latch Logic for Static Image Power Reduction
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Solution Overview
Problem
Conventional backlit LCDs require frame refresh, leading to high power consumption due to the need for continuous operation of scan lines and data lines.
Innovation Solution
A display driving circuit with two latches and a logic control unit that selects one of four preset voltages for a pixel electrode based on input data voltages, allowing for reduced operation when displaying static images and enabling four grayscale levels per pixel, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional backlit LCD refresh operation is used, then display function is maintained, but power consumption is high
Solution Approach 1:
The patent implements periodic action by enabling refresh operations only when necessary (when image content changes) rather than continuously refreshing every frame. The driving circuit detects whether the current frame differs from the previous frame and performs refresh operations only when a change is detected, thereby converting continuous periodic refresh into conditional periodic refresh that reduces power consumption while maintaining display functionality.
Solution Approach 2:
The patent applies dynamics by making the refresh operation dynamic and adaptive based on content changes. The driving circuit dynamically adjusts whether to perform refresh operations based on real-time detection of image content changes, transitioning from a static fixed-refresh-rate approach to a dynamic content-aware approach that optimizes power consumption according to actual display needs.
2Use of energy by moving object
If MIP circuit is disposed in pixels, then power consumption is reduced for static images, but applicability is limited to total reflection LCD and OLED panels
Solution Approach 1:
The patent achieves universality by designing a driving circuit that can be applied to multiple panel types including backlit LCD, total reflection LCD, and OLED panels. The circuit uses a content change detection mechanism that is panel-agnostic, allowing the same design to reduce power consumption across different display technologies without requiring MIP circuit integration specific to certain panel types.
Solution Approach 2:
The patent introduces an intermediary content change detection mechanism that mediates between the data input and the pixel driving. This intermediary layer detects whether refresh is needed and controls the timing of pixel updates, serving as a universal interface that works across different panel types without requiring panel-specific MIP circuit modifications.
3Reliability
If continuous refresh operation is performed, then display update capability is maintained, but data lines and scan lines must continuously operate
Solution Approach 1:
The patent implements periodic action by enabling data lines and scan lines to operate only periodically when content changes occur, rather than continuously. The driving circuit monitors for content changes and triggers line operations only when necessary, converting continuous line operation into conditional periodic operation that maintains display update capability while reducing energy consumption from continuous line activity.
Solution Approach 2:
The driving circuit performs self-service by automatically detecting content changes and autonomously deciding when refresh operations are needed. This self-monitoring and self-control mechanism eliminates the need for continuous external control signals, allowing the system to maintain display update capability while minimizing unnecessary operation of data lines and scan lines through intelligent self-regulation.
Data Source
AI summary
A display driving circuit and a pixel structure are provided. The driving circuit includes a first latch, a second latch and a logic control unit. The logic control is used for selecting to output one of four preset voltages to a pixel electrode via a voltage output end based upon a first data voltage and a second data voltage input by two logic control ends.