Display Driving Circuit Timing Synchronization
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Solution Overview
Problem
Display apparatuses experience luminance deviations between even and odd rows of pixels, affecting image quality due to inconsistencies in gate signal timing and voltage synchronization.
Innovation Solution
A driving circuit comprising multiple stages configured to output gate signals with synchronized rising edge timings for different periods in a frame period, including a first period for data supply, a second period for transistor initialization, and a third period for threshold voltage compensation, minimizing luminance deviations by adjusting clock signal timings and signal widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate signals are output with standard timing for data supply, then data can be supplied to the pixel, but luminance deviation occurs between odd and even pixel rows
Solution Approach 1:
The gate signal output is divided into multiple independent driving circuits (first, second, and third driving circuits) that operate in different periods. The first driving circuit handles data supply in the first period, while the second and third driving circuits perform initialization and threshold voltage compensation in subsequent periods. This segmentation allows each circuit to be optimized for its specific function, resolving the contradiction between efficient data supply and luminance uniformity.
Solution Approach 2:
The second driving circuit performs transistor initialization and the third driving circuit performs threshold voltage compensation before the main data supply operation. By performing these actions in advance in the second and third periods, the system ensures that the pixel circuit is fully prepared and calibrated before data is supplied, eliminating luminance deviations while maintaining data supply efficiency.
2Manufacturing precision
If multiple driving circuits operate in different periods, then luminance deviation is minimized, but device complexity increases
Solution Approach 1:
Each driving circuit is designed to handle multiple functions across different periods. The first driving circuit outputs gate signals for data supply in the first period, while the second and third driving circuits handle initialization and compensation in subsequent periods. This multi-functional design reduces the need for separate dedicated circuits for each function, thereby minimizing the increase in device complexity while achieving luminance uniformity.
Solution Approach 2:
The driving circuits operate in a periodic manner with distinct time slots (first period for data supply, second period for initialization, third period for compensation). This periodic operation allows each circuit to be simple and specialized for its specific function, rather than requiring a complex all-purpose circuit. The time-division multiplexing approach reduces overall device complexity while maintaining high luminance uniformity.
Data Source
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Figure 2
AI summary
A driving circuit to drive a display apparatus includes first through third driving circuits to respectively receive first through third clock signals for respectively outputting a first gate signal with a gate-on voltage synchronized with rising edge timing of the corresponding clock signal in a first period in which data is supplied to the pixel in a frame period, a second gate signal with a gate-on voltage synchronized with rising edge timing of the corresponding clock signal in a second period for initializing a transistor of the pixel in the frame period, and a third gate with a gate-on voltage synchronized with rising edge timing of the corresponding clock signal in a third period for compensating for a threshold voltage of the transistor in the frame period. The rising edge timing of the second clock signal is different from the rising edge timing of the third clock signal.