Display Driving Module Clock Signal Voltage Adjustment
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Solution Overview
Problem
Large display panels face issues with gate driving signal attenuation at the far end, leading to low charging rates and non-uniform display due to increased load, resulting in dark pixels and horizontal stripes.
Innovation Solution
A display driving module with a clock signal generating circuit and gate driving circuit that provides different clock signals in a time-sharing manner, generating gate driving signals with varying valid voltages to improve charging uniformity and prevent horizontal stripes by adjusting voltage potentials across the display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the display panel size and resolution are increased, then the display quality is improved, but the gate driving signal attenuation increases and charging uniformity deteriorates
Solution Approach 1:
The gate driving circuit is divided into multiple stages, with each stage responsible for driving a specific region of the display panel. This segmentation allows each stage to operate independently with optimized voltage levels, preventing signal attenuation across the entire panel while maintaining high resolution and display quality.
2Device complexity
If a single clock signal voltage level is used, then the circuit design is simple, but the far-end charging rate is low and horizontal stripes appear
Solution Approach 1:
The system dynamically adjusts the clock signal voltage level based on the operating region. Different voltage levels are applied to different stages of the gate driving circuit according to their specific requirements, optimizing the charging rate for each region while preventing horizontal stripe artifacts, thereby improving overall productivity without excessive complexity.
3Manufacturing precision
If the display panel operates under heavy load, then the resolution is maintained, but the gate driving signal is significantly attenuated at the far end
Solution Approach 1:
Different voltage levels are applied to different regions of the gate driving circuit based on their specific needs. The far-end stages receive higher voltage levels to compensate for signal attenuation, while near-end stages operate at lower voltages. This local optimization maintains high resolution under heavy load while ensuring adequate signal strength throughout the entire panel.
Data Source
AI summary
A display driving module, a display driving method, and a display device are provided. The display driving module includes a clock signal line, a clock signal generating circuit and a gate driving circuit, where the gate driving circuit includes multiple stages of gate driving units; the clock signal generating circuit is electrically connected to the clock signal line and is configured to generate at least two clock signals and provide different clock signals to the clock signal line in a time-sharing manner; the gate driving unit is electrically connected to the clock signal line and configured to generate a gate driving signal according to the clock signals on the clock signal line; when potentials of the clock signals are valid voltages, the potentials of different clock signals are different.