Display Panel Driving Circuit Mode Switching for High-Speed Link Recovery
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Solution Overview
Problem
The increasing number of pixels and frame rates in display panels leads to a surge in data communication demands, necessitating improved data communication efficiency and accuracy while minimizing power consumption and reducing the risk of erroneous operations due to communication errors.
Innovation Solution
A display driving device employing a low-speed communication circuit for configuration data, a high-speed communication circuit for image and control data, and a control circuit to switch operation modes based on detected abnormalities, along with a circuit to control pixel driving, ensuring data validity and synchronization across different modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed communication is used to transmit image data, then data transmission speed is improved, but the risk of communication errors increases
Solution Approach 1:
The patent applies preliminary action by performing clock signal training before actual high-speed data transmission. The communication clock signal is trained in advance to establish proper synchronization and timing parameters, ensuring that the high-speed communication can proceed with minimized errors. This preliminary training phase allows the system to optimize communication parameters before transmitting critical image data.
Solution Approach 2:
The patent implements feedback mechanisms through abnormal state detection during high-speed communication. When communication errors are detected, the system provides feedback by switching back to low-speed mode for re-transmission or re-initialization. This feedback loop enables the system to adapt to communication quality variations and maintain reliability despite operating at high speeds.
2Use of energy by moving object
If low-speed communication mode is used, then power consumption is reduced, but data transmission efficiency decreases
Solution Approach 1:
The patent applies dynamics by implementing dynamic mode switching between low-speed and high-speed communication circuits based on operational requirements. The control circuit automatically selects the appropriate communication mode: low-speed mode during initialization and configuration phases to minimize power consumption, and high-speed mode during active image data transmission to maximize efficiency. This dynamic adaptation allows the system to optimize the trade-off between power consumption and transmission efficiency in real-time.
3Productivity
If high-speed communication is implemented, then data communication performance is improved, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the communication system into distinct functional modules: a low-speed communication circuit for initialization and control, a high-speed communication circuit for image data transmission, and a control circuit for mode switching. This segmentation allows each module to be optimized independently and simplifies the overall system architecture by clearly defining the responsibilities and interfaces of each component, thereby managing complexity while achieving high performance.
4Reliability
If mode switching is implemented for error recovery, then communication reliability is improved, but switching time is added
Solution Approach 1:
The patent applies this principle by implementing a streamlined error recovery mechanism that uses low-speed communication mode as a temporary, disposable fallback when high-speed communication fails. Rather than attempting complex error correction in high-speed mode, the system quickly switches to the simpler, more reliable low-speed mode for re-transmission or re-initialization. This approach accepts the time penalty of mode switching as a worthwhile trade-off for ensuring communication reliability, using the low-speed mode as a reliable but time-consuming backup option.
Data Source
AI summary
A display driving device includes a low-speed communication circuit configured to receive configuration data at a first data rate in a first mode; a high-speed communication circuit configured to train a communication clock signal for communication at a second data rate in a second mode, to receive image data and first control data using the communication clock signal in a third mode, and to receive second control data using the communication clock signal in a fourth mode; a control circuit configured to switch the first mode to the second mode upon completion of the first mode, to switch the second mode to the third mode upon completion of the second mode, to switch the third mode to the second mode when an abnormal state is detected in the third mode, and to switch the fourth mode to the first mode when an abnormal state is detected in the fourth mode; and a circuit configured to control pixels of a display panel to be driven according to the image data, thereby easily managing operation modes of a data driving device and a data processing device and minimizing a recovery time when an error occurs.