Display Data Driving Circuit for Stable High-Speed Mode Switching
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Solution Overview
Problem
As display panels with higher resolutions and increased pixel counts require faster data communication to process increased image data, existing technologies face challenges in speeding up data communication while maintaining accuracy and reliability, particularly in transitioning between low-speed and high-speed communication modes.
Innovation Solution
The implementation of a data driving device with low-speed and high-speed communication circuits, a lock control circuit, and clock recovery circuits to manage communication modes, ensuring seamless transitions and maintaining lock signals for stable data transfer, along with an equalizer tuning mechanism for optimizing high-speed communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed communication mode is used to increase data transmission speed, then data communication speed is improved, but communication stability and reliability deteriorate during mode transitions
Solution Approach 1:
The patent performs low-speed clock training before switching to high-speed communication mode. This preliminary action ensures that the communication circuits are properly synchronized and stable before increasing the data transmission speed, thereby preventing communication failures during mode transitions.
Solution Approach 2:
The patent dynamically switches between low-speed and high-speed communication modes based on operational requirements. The system can transition from low-speed mode (with higher stability) to high-speed mode (with faster data transmission) and back, allowing optimal performance for different operational phases while maintaining overall reliability.
2Reliability
If low-speed communication mode is used to ensure communication stability, then communication reliability is improved, but data communication speed deteriorates
Solution Approach 1:
The patent divides the communication process into distinct segments: low-speed clock training phase and high-speed data transmission phase. Each phase uses the appropriate speed mode - low-speed for stability-critical operations and high-speed for data-intensive operations - thereby optimizing both reliability and speed across different operational contexts.
3Measurement precision
If clock training is performed repeatedly to improve communication accuracy, then measurement precision is improved, but time consumption increases
Solution Approach 1:
The patent performs clock training in advance during the low-speed communication phase before transitioning to high-speed mode. This preliminary clock training ensures that synchronization is established beforehand, eliminating the need for repeated training during high-speed operations and reducing overall time consumption.
Solution Approach 2:
The patent maintains communication continuity by performing clock training during the low-speed phase without interrupting the overall communication flow. The training process is integrated into the normal operation sequence, ensuring that useful actions (data transmission) continue without significant interruptions while still achieving the desired precision.
Data Source
AI summary
The present disclosure relates to a data processing device, a data driving device, and a system for driving a display device, and more particularly, to a data processing device, a data driving device, and a system for speeding up data communication in a display device.