Display Device Driving Voltage Line Intermediary

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Solution Overview

Problem

Display devices face issues with parasitic capacitance and horizontal crosstalk due to the proximity of initialization voltage and data lines, which degrade display quality.

Innovation Solution

The display device design includes a substrate with pixel circuit areas, an initialization voltage line, a driving voltage line adjacent to the initialization voltage line, and data lines spaced apart with the driving voltage line in between, reducing parasitic capacitance and improving display quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the initialization voltage line and data line are disposed close to each other, then the device complexity is reduced, but parasitic capacitance increases causing display quality deterioration

Engineering Contradiction:
Improveline arrangement complexityVSAvoidparasitic capacitance
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

A driving voltage line is introduced as an intermediary element between the initialization voltage line and the data line. This intermediate line acts as a buffer that reduces the direct electromagnetic coupling between the initialization voltage line and data line, thereby decreasing parasitic capacitance while maintaining a relatively compact overall layout.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent utilizes multi-layer routing where lines are arranged in different vertical layers rather than only in the same plane. By distributing the initialization voltage line, driving voltage line, and data line across different layers with appropriate spacing, the parasitic capacitance is reduced while maintaining planar integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-affected harmful factors

If the initialization voltage line and data line are spaced apart, then parasitic capacitance is reduced, but the device area increases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidpixel circuit area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The driving voltage line serves as a space-efficient intermediary that allows the initialization voltage line and data line to be positioned closer than would be possible without it, while still maintaining adequate electrical isolation. This achieves parasitic capacitance reduction with minimal area penalty.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The driving voltage line performs multiple functions: it provides driving voltage to the pixel circuit and simultaneously acts as an isolation barrier between the initialization voltage line and data line. This multi-functionality reduces the need for separate isolation structures, optimizing area utilization.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If the initialization voltage line and data line are close, then manufacturing precision requirements are reduced, but horizontal crosstalk increases

Engineering Contradiction:
Improveline positioning toleranceVSAvoidhorizontal crosstalk
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The driving voltage line acts as an electromagnetic shield between the initialization voltage line and data line, reducing signal coupling and horizontal crosstalk. This allows for more relaxed manufacturing tolerances while maintaining signal integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250104635A1Display device
Publication Date: 2025.03.27 SAMSUNG DISPLAY CO LTD
  • US20250104635A1 patent drawing
  • US20250104635A1 patent drawing
  • US20250104635A1 patent drawing

AI summary

A display device includes a substrate including first to N-th pixel circuit areas, where N is a natural number greater than 1 disposed in a first direction, an initialization voltage line disposed on the substrate, the initialization voltage line extending in a second direction, intersecting the first direction, and overlapping one of the first to N-th pixel circuit areas, a driving voltage line disposed on the substrate, the driving voltage line extending in the second direction, and adjacent to the initialization voltage line in the first direction, and a data line disposed on the substrate, the data line extending in the second direction, and spaced apart from the initialization voltage line in the first direction with the driving voltage line disposed between the data line and the initialization voltage line.