Display Electrode Layout With Stacked Node Connection for Dead Space Reduction
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Solution Overview
Problem
Existing display apparatuses face challenges in achieving improved display quality as they become thinner and lighter, necessitating innovative designs to enhance functionality and performance.
Innovation Solution
The display apparatus incorporates specific transistor configurations, including a first and second transistor with gate electrodes and semiconductor layers, a node electrode connecting the transistors, and conductive layers overlapping the node electrode, along with pixel electrodes disposed around the node electrode, to optimize electrical connections and enhance display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If display apparatuses are made thinner and lighter, then portability and versatility are improved, but display quality and functionality are compromised
Solution Approach 1:
The patent introduces a multi-layered electrode structure with conductive layers stacked in the vertical dimension (first conductive layer, second conductive layer, node electrode at different heights). This three-dimensional arrangement allows improved electrical connections and signal transmission quality without increasing the horizontal footprint, thereby maintaining thin profile while enhancing display performance
Solution Approach 2:
The patent implements nested conductive layers where the first conductive layer and second conductive layer are positioned at different heights and overlap in plan view, with the node electrode connecting them vertically. This nested arrangement maximizes the use of vertical space to improve electrical connectivity without adding horizontal bulk, resolving the contradiction between thinness and display quality
2Ease of manufacture
If conventional electrode arrangements are used, then manufacturing is simpler, but dead space increases and display area utilization decreases
Solution Approach 1:
The patent moves electrode connections from a two-dimensional planar arrangement to a three-dimensional stacked configuration. The node electrode vertically connects the first and second conductive layers, allowing signals to pass through the vertical dimension rather than requiring lateral routing. This reduces dead space and improves display area utilization while maintaining manufacturing feasibility through standard layered deposition processes
Solution Approach 2:
The patent merges multiple conductive functions into a compact vertical stack at the node electrode location. The first conductive layer, second conductive layer, and node electrode are combined in a small vertical volume, eliminating the need for extended lateral connections. This consolidation reduces dead space and improves display area utilization while the layered structure maintains electrical functionality
Data Source
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AI summary
Disclosed in one embodiment of the present invention is a display device comprising: a first transistor including a first gate electrode and a first semiconductor layer, a second transistor including a second gate electrode and a second semiconductor layer, a node electrode for connecting the first transistor and the second transistor; a first conductive layer, which is arranged on the node electrode and overlaps the node electrode; and a pixel electrode, which is arranged on the first conductive layer and is arranged in the vicinity of the node electrode.