Display Panel Electrode Opening for Signal Stability
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Solution Overview
Problem
Horizontal lines appear in in-plane display images due to differences in capacitance between clock signal lines, connection lines, and a second electrode in conventional display panels, particularly affecting ultra-high resolution products.
Innovation Solution
A display panel design featuring a first electrode with openings corresponding to clock signal lines and connection lines, reducing the capacitance difference between these components, thereby minimizing signal delay and improving image stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional common electrode is used that covers the entire surface of the color filter substrate, then the display structure is simple and complete, but different capacitances are formed between clock signal lines, connection lines, and the electrode, causing signal delay and horizontal lines in the display image
Solution Approach 1:
The common electrode is segmented by introducing openings at specific positions where clock signal lines and connection lines are located. This divides the electrode into multiple regions, allowing different capacitance values to be formed at different locations. The openings create distinct electrical environments that compensate for the varying lengths and areas of the signal lines, thereby equalizing the overall capacitance and eliminating signal delay issues.
Solution Approach 2:
Different regions of the common electrode are given different properties by strategically placing openings at specific locations. The openings are positioned corresponding to clock signal lines and connection lines with different lengths, creating local capacitance variations that compensate for the inherent differences in line dimensions. This local modification allows the electrode to have different electrical characteristics at different positions, achieving overall capacitance equalization.
2Reliability
If the electrode covers the clock signal lines and connection lines completely, then the electrical connection is stable, but the capacitance difference between different signal lines increases, causing horizontal lines in the display
Solution Approach 1:
The openings in the common electrode extract or remove the electrode material at specific positions corresponding to clock signal lines and connection lines. This extraction creates a reduction in the electrode's coverage area at these locations, which directly reduces the capacitance formed between the electrode and the signal lines. By selectively removing the electrode material, the patent compensates for the varying capacitances caused by different signal line lengths and areas.
3Reliability
If openings are introduced in the electrode to reduce capacitance difference, then signal delay is reduced and horizontal lines are eliminated, but the electrode structure becomes more complex
Solution Approach 1:
The common electrode is segmented by introducing openings at specific positions where clock signal lines and connection lines are located. This divides the electrode into multiple regions, allowing different capacitance values to be formed at different locations. The openings create distinct electrical environments that compensate for the varying lengths and areas of the signal lines, thereby equalizing the overall capacitance and eliminating signal delay issues.
Data Source
AI summary
The present application provides a display panel. The display panel includes: gate driver on array (GOA) units arranged along a first direction; clock signal lines arranged along a second direction and arranged at one side of the GOA units; the connection lines, each of the connection lines being extended along the second direction and connected between the corresponding clock signal line and the corresponding GOA units; and a first electrode arranged at one side of the GOA units, the clock signal lines, and the connection lines. The first electrode includes an opening, and the opening is arranged corresponding to at least one of the clock signal lines and/or at least one of the connection lines.