Display Pixel Electrode Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
As liquid crystal display devices increase in size and resolution, the need for high-speed operation and reduced parasitic capacitance becomes critical to maintain display quality and reduce power consumption, as conventional designs suffer from signal transmission delays and increased power usage due to parasitic capacitance between wirings.
Innovation Solution
The design incorporates a semiconductor film with In, M (aluminum, gallium, yttrium, or tin) oxides, and a specific electrode structure where the semiconductor film is in contact with electrodes, reducing parasitic capacitance by overlapping regions and optimizing the gate insulating film and transistor composition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the screen size and resolution are increased, then the display quality is improved, but the parasitic capacitance between wirings increases causing signal transmission delay
Solution Approach 1:
The patent applies dimensionality change by configuring the first electrode to overlap with the scan line in the planar layout, thereby utilizing the vertical dimension (thickness direction) to reduce parasitic capacitance. This overlapping configuration shortens the signal transmission path through the semiconductor film, effectively reducing the harmful parasitic capacitance effect while maintaining the large screen size and high resolution display quality.
2Measurement precision
If the screen size and resolution are increased, then the display quality is improved, but the power consumption increases due to parasitic capacitance
Solution Approach 1:
The patent reduces power consumption by configuring the first electrode to overlap with the scan line, which shortens the signal transmission path through the semiconductor film. This dimensional configuration reduces parasitic capacitance, thereby decreasing the energy required for signal transmission and reducing overall power consumption in large-sized, high-resolution display devices.
3Speed
If high-speed driving is implemented, then the display quality and response speed are improved, but the transistor requires higher on-state current and operating speed
Solution Approach 1:
The patent extracts and addresses the parasitic capacitance component separately by configuring the first electrode to overlap with the scan line. This configuration isolates and reduces the parasitic capacitance effect, allowing the transistor to achieve high-speed driving with lower on-state current requirements, as the harmful capacitance is minimized through the overlapping structure.
Data Source
AI summary
A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided.The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film. The signal line intersects with the scan line, the first electrode is electrically connected to the signal line, the first electrode has a region overlapping with the scan line, the second electrode faces the first electrode, the third electrode faces the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is provided between the scan line and the first electrode to the third electrode.