Display Engine Frame Rate Synchronization Power Reduction

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Solution Overview

Problem

Current display technologies face inefficiencies and high power consumption when presenting video content with a native frame rate different from the display's refresh rate, requiring redundant operations and translator functions that increase power usage, especially in mobile devices.

Innovation Solution

The system optimizes power consumption by modifying the graphics logic and display engine operations to synchronize data frame rendering and transmission with the native frame rate, allowing components to enter a low power mode during idle periods, reducing redundant data transfers and storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If the display refresh rate is increased to 60 Hz or higher, then the perceived video smoothness and flicker reduction are improved, but the power consumption increases due to redundant frame repetitions and multiple translator operations

Engineering Contradiction:
Improveperceived video smoothnessVSAvoidpower consumption
Core Design Contradiction:
Illumination intensityVSUse of energy by moving object

Solution Approach 1:

The patent combines the display engine and timing controller into an integrated display interface that directly accesses frame buffer memory, eliminating redundant translator operations between separate components. This merging reduces the number of processing stages while maintaining 60 Hz refresh capability, thereby lowering power consumption without sacrificing video smoothness.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The display engine performs frame rendering and prepares pixel data in advance before the refresh cycle begins. By pre-processing frames and staging data in buffer memory ahead of time, the system avoids last-minute processing during the refresh window, reducing active processing time and power consumption during critical display updates.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If multiple translator functions are performed to accommodate frame rate differences, then the compatibility between different frame rates is improved, but the device complexity and power consumption increase

Engineering Contradiction:
Improveframe rate compatibilityVSAvoidtranslator functionality
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The integrated display interface is designed to handle multiple frame rates (24 Hz, 30 Hz, 60 Hz, and variable refresh rates) through a single unified architecture. The display engine dynamically adjusts its operation mode based on the source frame rate without requiring separate translator components, simplifying the system while maintaining broad compatibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically changes operational parameters such as pixel clock frequency, data bus width, and processing timing based on the detected frame rate. By adjusting these parameters rather than using fixed translator stages, the system adapts to different frame rates with a single flexible interface, reducing complexity while preserving adaptability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If redundant memory reads and writes are performed during frame data transmission, then the data integrity is maintained, but the power consumption and processing overhead increase

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the frame data directly from the frame buffer memory to the display interface in a single read operation, eliminating redundant intermediate memory writes and reads. By taking the data extraction path directly without unnecessary storage cycles, the system maintains data integrity through direct transmission while significantly reducing the power consumption associated with repeated memory access operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10199014B2Method and apparatus for managing image data for presentation on a display
Publication Date: 2019.02.05 INTEL CORP
  • US10199014B2 patent drawing
  • US10199014B2 patent drawing
  • US10199014B2 patent drawing

AI summary

An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.