Display EPI Clock and Line-Pair Scaling for VRR Power Control
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Solution Overview
Problem
Existing display devices face challenges in efficiently managing power consumption and extending their lifespan by adapting to varying image types and refresh rates, particularly in variable refresh rate (VRR) modes.
Innovation Solution
A display device and method that adaptively changes the embedded clock P-P interface (EPI) pair options and internal clock frequency based on driving frequency, optimizing the EPI clock for active and vertical blank periods, and adjusting the number of EPI line pairs to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the display device operates at high refresh rates to maintain image quality and responsiveness, then display performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic refresh rate adjustment based on image content analysis. The system transitions from fixed refresh rates to variable refresh rates where the refresh rate is dynamically modified according to the complexity and motion content of displayed images, allowing the display to operate at higher refresh rates when needed and lower refresh rates when content is static, thereby reducing overall power consumption while maintaining display performance.
Solution Approach 2:
The patent changes the refresh rate parameter adaptively based on image characteristics. By analyzing image data to determine content complexity and motion levels, the system adjusts the refresh rate parameter in real-time, switching between different refresh rate modes (e.g., high refresh rate for dynamic content, low refresh rate for static content) to optimize the balance between display quality and energy consumption.
2Speed
If the EPI clock frequency is increased to match high driving frequencies, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts the EPI clock frequency according to the driving frequency and image content requirements. Instead of maintaining a fixed high clock frequency, the system varies the clock frequency in real-time based on whether high refresh rates are needed, thereby optimizing data transmission speed when required while minimizing power consumption during low-activity periods.
Solution Approach 2:
The patent modifies the EPI clock frequency parameter adaptively to match the driving frequency. When the driving frequency is high, the EPI clock frequency is increased to maintain fast data transmission. When the driving frequency is reduced, the EPI clock frequency is decreased accordingly, achieving energy-efficient operation without sacrificing transmission speed when needed.
3Productivity
If the number of EPI line pairs is increased to transmit data at high frequencies, then data transmission capability is improved, but device complexity increases
Solution Approach 1:
The patent dynamically selects the number of EPI line pairs to be activated based on the driving frequency and data transmission requirements. Instead of always using the maximum number of line pairs, the system adapively enables only the necessary number of line pairs for the current operating conditions, reducing interface complexity during low-frequency operation while maintaining full transmission capability when high refresh rates are required.
4Use of energy by moving object
If the EPI clock frequency is reduced for vertical blank periods to save power, then power consumption is reduced, but timing synchronization becomes more difficult
Solution Approach 1:
The patent implements periodic clock signals during vertical blank periods even at reduced frequencies. By maintaining periodic clock signals rather than completely stopping the clock, the system achieves low-power operation while preserving timing synchronization capabilities. The periodic action ensures that timing information is maintained at a reduced rate, allowing for proper synchronization during the low-frequency vertical blank period.
Data Source
AI summary
A display device in one example includes a display panel having pixels disposed therein, a timing controller configured to output an embedded clock P-P interface (EPI) data including an EPI clock, control data, and image data through one or more EPI line pairs, and a data driver connected to the timing controller through the one or more EPI line pairs. The data driver is configured to generate an internal clock based on the EPI clock, process the control data and the image data, and supply data voltages to the pixels. The timing controller changes a frequency of the EPI clock according to a driving frequency controlled by a host system. A method of driving the display device is also discussed.