Display Scanning Line Layout for Round-Edge ESD Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increased wiring length of scanning lines in display devices with round portions reduces the resistance to electrostatic discharge (ESD), leading to manufacturing yield reductions.
Innovation Solution
Incorporating semiconductor layers in the non-display area with varying numbers and configurations, covered by an insulating film, to distribute electrostatic charge and prevent dielectric breakdown, while maintaining different wiring lengths for scanning lines crossing round portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a round portion is added to the display area, then the display device achieves a novel shape and aesthetic appeal, but the wiring length of the scanning line increases and the resistance to electrostatic discharge decreases
Solution Approach 1:
The patent divides the non-display area into multiple regions and places dummy pixels at different locations (e.g., four corners) to segment the ESD protection function. Each dummy pixel with its semiconductor layer acts as an independent charge distribution point, collectively providing comprehensive ESD protection for the extended scanning lines caused by the round portion.
Solution Approach 2:
The dummy pixels with semiconductor layers serve as intermediary elements between the scanning lines and the ESD threat. These dummy pixels intercept and distribute electrostatic charge before it can reach and damage the active display area, acting as a protective buffer zone.
2Shape
If the wiring length of scanning lines is increased to accommodate a round portion, then the display area shape is enhanced, but the resistance to electrostatic discharge is reduced leading to manufacturing yield reduction
Solution Approach 1:
The dummy pixels are pre-configured in the non-display area during the manufacturing process to establish ESD protection pathways before actual ESD events occur. The semiconductor layers are positioned in advance to ensure optimal charge distribution capability for the specific round portion geometry.
Solution Approach 2:
The patent applies ESD protection measures specifically in the non-display area where dummy pixels are located, rather than uniformly across the entire display. This localized approach targets the specific regions where extended wiring creates ESD vulnerability, preserving manufacturing yield without affecting the overall display quality.
3Reliability
If dummy pixels are arranged in the non-display area with semiconductor layers, then ESD resistance is improved, but the device complexity increases
Solution Approach 1:
The dummy pixels in the non-display area serve multiple functions: they act as ESD protection elements, provide charge distribution pathways, and maintain structural consistency with the active display area. This multi-functionality reduces the need for separate dedicated ESD protection structures, thereby limiting the increase in device complexity.
Solution Approach 2:
The ESD protection function is merged with the existing dummy pixel structure in the non-display area. Rather than adding separate ESD protection components, the patent combines ESD functionality into the dummy pixels, which already occupy the non-display space, thus minimizing additional structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances ESD resistance and suppresses manufacturing yield reductions by balancing charge distribution across scanning lines, even with varying wiring lengths.
Implementation Method 1
A breakdown caused by electrostatic discharge (ESD) in the display device leads to reduction in a manufacturing yield
Implementation Method 2
prevent dielectric breakdown
Data Source
AI summary
According to one embodiment, a display device includes first semiconductor layers crossing a first scanning line in a non-display area, the first semiconductor layers being a in number, second semiconductor layers crossing a second scanning line in the non-display area, the second semiconductor layers being b in number, and an insulating film disposed between the first and second semiconductor layers and the first and second scanning lines, wherein a and b are integers greater than or equal to 2, and a is different from b, and the first and second semiconductor layers are both entirely covered with the insulating film.