Display Panel Fan-Out Layer Layout for Seamless Tiled Screens
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Solution Overview
Problem
Large-size displays require splicing multiple panels, which results in visible gaps and a sense of image discontinuity due to non-display regions where fan-out lines are located, necessitating a design that minimizes these gaps.
Innovation Solution
The fan-out lines are arranged in a conductive layer separate from the data lines, overlapping pixels to reduce the non-display region and increase the display-to-substrate ratio, with the fan-out lines connected to driving elements via a flexible printed circuit board on the substrate's side surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If fan-out lines are arranged in the same layer as data lines, then routing is simpler, but the non-display region area increases causing visible gaps
Solution Approach 1:
The fan-out lines are moved from the same plane as data lines to a different conductive layer, utilizing the third dimension (layer stacking) to resolve the spatial conflict. This allows fan-out lines to overlap with pixel regions in the top view while being electrically isolated in the vertical dimension, thereby reducing the non-display region area and eliminating visible gaps without causing short circuits.
2Area of stationary object
If fan-out lines are placed in a separate conductive layer overlapping pixels, then the display-to-substrate ratio increases, but the risk of electrical interference with data lines increases
Solution Approach 1:
By transitioning to multi-layer conductive structure, the patent places fan-out lines and data lines in different vertical layers, allowing their projections to overlap in the horizontal plane without physical contact. This spatial separation in the vertical dimension enables both high display-to-substrate ratio and reliable electrical isolation simultaneously.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the fan-out lines and data lines in different conductive layers. These insulating layers act as mediators that prevent electrical interference while allowing the fan-out lines to overlap with pixel regions, thus enabling both compact layout and electrical reliability.
3Ease of operation
If fan-out lines are routed through larger non-display regions, then routing is easier, but the sense of image discontinuity increases
Solution Approach 1:
The patent utilizes vertical layering to allow fan-out lines to traverse through the display region's vertical space rather than being constrained to horizontal routing in the non-display region. This enables the fan-out lines to pass over pixel regions without disrupting the visual display, maintaining image continuity while providing routing flexibility in the vertical dimension.
Data Source
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AI summary
A display device (10) includes a substrate (100), a first signal line (DL1) disposed on the substrate (100), and a first pixel (PU12) including a first transistor (202) having a gate electrode (GE), a source electrode (S) and a drain electrode (D), wherein the source electrode (S) is electrically connected to the first signal line (DL1) . The display device (10) includes a fan-out line (FL1) electrically connected to the first signal line (DL1), wherein the fan-out line (FL1) partially overlaps the first pixel (PU12) and is formed in a layer (CL3) different from layers (CL1, CL2)of the gate electrode (GE), the source electrode (S) and the drain electrode (D).