Display Panel Fan-Out Shielding for Parasitic Capacitance Control
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Solution Overview
Problem
Display panels using FIAA technology experience display abnormalities due to parasitic capacitance caused by overlaps between fan-out traces and thin film transistor gates, leading to signal interference.
Innovation Solution
Incorporating a shielding portion in the conductor layer between the fan-out traces and the thin film transistor gates, with a specific spacing arrangement to minimize parasitic capacitance and prevent signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fan-out traces are located in the display area to reduce lower border width, then manufacturing cost is reduced and process difficulty is lowered, but parasitic capacitance is generated causing display abnormality
Solution Approach 1:
A shielding portion is introduced as an intermediary element between the fan-out trace and the thin film transistor gate. This shielding portion is configured to overlap the fan-out trace and is electrically connected to a reference potential, thereby intercepting and redirecting the electromagnetic field from the fan-out trace away from the gate, reducing parasitic capacitance coupling while allowing the fan-out trace to remain in the display area
2Device complexity
If fan-out traces overlap with thin film transistor gates in the thickness direction, then routing is simplified and cost is reduced, but parasitic capacitance interferes with data signals causing abnormal display
Solution Approach 1:
The shielding portion is strategically positioned to overlap both the fan-out trace and the gate area. By being electrically connected to a reference potential, it converts the harmful electromagnetic field from the fan-out trace into a controlled field that terminates at the shielding portion, preventing it from coupling with the gate and causing interference
Solution Approach 2:
The shielding portion serves as a mediator that intercepts the electromagnetic field from the fan-out trace before it can couple with the gate. It provides a controlled path for the field, reducing parasitic capacitance while maintaining the simplified routing structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and improves display quality by ensuring that the shielding portion's spacing with the gate is larger than with the fan-out trace, thereby preventing signal distortion.
Implementation Method 1
overlaps between gates of thin film transistors and fan-out traces in a display area in a thickness direction of the display panel, thereby generating parasitic capacitances, causing interference to data signals
Data Source
AI summary
Embodiments of the present application disclose a display panel and a display device, the display panel including a substrate and a thin film transistor layer, the thin film transistor layer including a first thin film transistor, a first conductor layer, and a fan-out trace. Orthographic projections of a first fan-out sub-section, a first gate, and a first conductor layer on the substrate at least partially overlap. And a spacing between a first shielding portion and the first gate is greater than a spacing between the first shielding portion and the first fan-out sub-section.