Display Logic Circuit for Streaming Fresnel Lens Values
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing holographic projector systems face inefficiencies in calculating Fresnel lens values, requiring numerous multiplications for each pixel, which is resource-intensive and demanding, especially in real-time holographic projection systems.
Innovation Solution
A logic circuit is developed that reduces the number of multiplications needed to calculate Fresnel lens values by using arithmetic progression and addition functions instead of multiplication functions, specifically designed for field-programmable gate arrays or similar devices, to provide a continuous stream of Fresnel lens values for holographic projection systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional multiplication functions are used to calculate Fresnel lens values for each pixel, then calculation precision is maintained, but processing time and resource consumption increase significantly
Solution Approach 1:
The patent transforms the calculation parameter from multiplication operations to addition operations. By using the property that n² = (n-1)² + 2n - 1, the circuit calculates square values through iterative addition, fundamentally changing the computational parameter from multiplicative to additive, thereby reducing processing time while maintaining precision
Solution Approach 2:
The circuit pre-calculates and stores square values of integers in a lookup table during system initialization. When Fresnel lens values are needed, the pre-computed square values are directly retrieved and used in the calculation formula, eliminating the need for real-time multiplication operations
2Reliability
If numerous multiplication operations are performed for each Fresnel lens value, then accurate holographic projection is achieved, but device complexity and resource demands increase
Solution Approach 1:
The patent replaces complex multiplication operations with simpler addition operations in the logic circuit. By substituting the mechanical/computational complexity of multiplication with the simpler operation of addition, the circuit achieves the same mathematical result with reduced complexity and fewer logic gates
Solution Approach 2:
The calculation of Fresnel lens values is segmented into independent pixel processing units. Each pixel's Fresnel value is calculated separately using the simplified addition-based square calculation, allowing parallel processing and reducing overall system complexity while maintaining accuracy
3Adaptability or versatility
If real-time holographic projection is implemented, then dynamic display capability is improved, but processing speed requirements increase due to traditional calculation methods
Solution Approach 1:
The circuit implements continuous generation of Fresnel lens values through an iterative addition process that continuously produces the next square value in sequence. This continuous action enables real-time holographic projection by maintaining a steady stream of calculated values without interruption or batch processing
Solution Approach 2:
The calculation follows a periodic pattern where square values are generated in sequential order (1², 2², 3², ...) through repeated addition cycles. This periodic generation of values synchronizes with the display refresh rate, enabling smooth real-time holographic projection
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A logic circuit comprising a logic sub-circuit arranged to output a stream, S1, of Fresnel lens values, F(x), of a Fresnel lens for display on [m × n] pixels of a pixelated display device. In a first step, the logic circuit is arranged to set an initial data value stored in a first data register unit of the logic sub-circuit to (a - k)2 and set an initial data value stored in a second data register unit of the logic sub-circuit to a2 - (a - k)2. In a second step the logic circuit is arranged to read the initial data value stored in the first data register unit and the initial data value stored in the second data register unit in a first iteration, and to read the data value stored in the first data register unit in the preceding iteration and the data value stored in the second data register unit in the preceding iteration, in a further iteration. In a third step, the logic circuit is arranged to sum the data value read from the first data register unit and the data value read from the second data register unit to form x2. In a fourth step, the logic circuit is arranged to calculate F(x) based on x2. In a fifth step, the logic circuit is arranged to output F(x) as the next value in the stream of F(x) values. In a sixth step, the logic circuit is arranged to write x2 to the first data register unit. In a seventh step, the logic circuit is arranged to add 2k2 to the value stored in the second data register unit. In an eighth step, the logic circuit is arranged to perform further iterations that repeat the second to seventh steps for x = a + k, a + 2k, a + 3k ... a + (n - 1)k, wherein a is the starting value of x, k is an increment in x and F(a) is the first value of stream, S1.