Display Panel Gate Timing for Lower Blank-Period Power
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Solution Overview
Problem
Existing display devices face challenges in reducing power consumption and preventing degradation of display quality, particularly in the management of gate signals and emission control in display panels.
Innovation Solution
A display device with a gate driver that outputs specific gate signals and emission control signals with precise timing control, using a timing controller to toggle clock signals between logic levels during active periods and maintain certain signals at constant voltages during blank periods, optimizing the operation of thin film transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are continuously toggled during blank periods to maintain signal integrity, then display quality is preserved, but power consumption increases due to unnecessary switching operations
Solution Approach 1:
The patent applies periodic action by toggling clock signals only during active display periods and maintaining them at constant voltages during blank periods. The timing controller selectively enables clock signal toggling based on whether the current period is active or blank, thereby eliminating unnecessary switching operations during blank periods while ensuring proper signal operation during active periods.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the state of clock signals based on operational requirements. During active periods, clock signals are allowed to toggle to maintain display quality. During blank periods, the timing controller dynamically switches clock signals to constant voltage levels (logic high or logic low) to reduce power consumption while still maintaining adequate signal levels for the subsequent active period.
2Use of energy by moving object
If gate signals are maintained at constant voltage during blank periods, then power consumption is reduced, but signal integrity may degrade without proper timing control
Solution Approach 1:
The timing controller employs feedback mechanisms to monitor the display operation state and adjust clock signal behavior accordingly. By detecting whether the display is in an active or blank period, the timing controller provides appropriate feedback control to gate drivers, enabling them to maintain constant voltages during blank periods while ensuring proper signal transitions occur at the beginning of active periods, thus maintaining signal integrity without excessive power consumption.
3Reliability
If multiple clock signals are toggled during blank periods to maintain all gate signals, then display quality is preserved, but device complexity and power consumption increase
Solution Approach 1:
The timing controller implements multi-functionality by using a single control mechanism to manage multiple clock signals simultaneously. Rather than independently controlling each clock signal, the timing controller applies a unified approach where all clock signals are selectively toggled or held at constant voltages based on the display operation state, thereby reducing control complexity while maintaining display quality.
Data Source
AI summary
A display device includes: a display panel including a pixel connected to a first gate line, a second gate line, a third gate line, and a light emission control line; a gate driver; and a timing controller. The gate driver is to: output a first gate signal, a second gate signal, a third gate signal, and an emission control signal, each having a pulse, during an active period; and output the emission control signal having a pulse, while maintaining the first and second gate signals at a constant voltage, during a blank period. The timing controller is to: provide, to the gate driver during the active period, first to fourth clock signals that toggle between a logic high level and a logic low level; and maintain the first and second clock signals at a constant voltage during the blank period.