Display Panel Gate Driving Circuit Layout for Narrower Frames
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Solution Overview
Problem
The frame width of AMOLED display panels is determined by the arrangement of the gate driving circuit in the non-display area, limiting the potential for a narrower frame design.
Innovation Solution
The gate driving circuit is redesigned with a layout that includes a substrate with a gate driving circuit comprising a frame start signal line, clock signal line, inverted clock signal line, and shift register units, where transistors are formed by a continuous semiconductor layer with overlapping channel portions and conductive portions, allowing for efficient coupling and reduced area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate driving circuit is arranged in the non-display area, then the gate driving circuit can be isolated from the display area, but the frame width is increased due to the space required for the gate driving circuit
Solution Approach 1:
The patent transitions from a conventional planar arrangement where the gate driving circuit occupies horizontal space in the non-display area to a vertical arrangement where the gate driving circuit is stacked above the display area. This dimensional change allows the gate driving circuit to be positioned in the thickness direction rather than the planar direction, thereby reducing the frame width while maintaining circuit isolation and functionality
Solution Approach 2:
The patent implements a nested structure where the gate driving circuit is positioned within the vertical space above the display area. The shift register units are arranged in a stacked configuration, with each unit containing multiple transistors that are vertically integrated. This nesting approach allows the gate driving circuit to occupy the vertical dimension rather than expanding the horizontal frame width
2Ease of operation
If the shift register units are arranged in the non-display area, then the gate driving function is provided, but the area occupied by the gate driving circuit increases
Solution Approach 1:
The patent applies local quality by creating different functional zones within the gate driving circuit. The shift register units are divided into multiple stages, with each stage containing transistors with specifically optimized characteristics. The active layers of different transistors are positioned at different heights, allowing each transistor to be optimized for its specific function while maintaining compact overall dimensions
Solution Approach 2:
The patent utilizes the vertical dimension to reduce the planar area of the gate driving circuit. By stacking transistors and signal lines in the thickness direction, the circuit achieves three-dimensional integration that minimizes the horizontal footprint while maintaining all necessary gate driving functions
Data Source
AI summary
A display substrate includes a substrate and a gate driving circuit provided on the substrate; the gate driving circuit includes: a frame start signal line, a clock signal line, an inverted clock signal line, a first level signal line, a second level signal line, and a plurality of shift register units. The plurality of transistors at least include a first transistor, a second transistor, and a third transistor, active layers of the first, second and third transistors are formed by a continuous first semiconductor layer, the first semiconductor layer extends along a first direction; the first semiconductor layer includes at least three channel portions corresponding to the first transistor, the second transistor and the third transistor, and a conductive portion provided between adjacent channel portions, transistors corresponding to the adjacent channel portions are coupled to each other through a corresponding conductive portion.