Display Device Gate Clock Signal Recovery Mechanism

The patent applies preliminary action by calculating the gate clock reference time in advance based on the on-clock signal period and the number of gate clock signals, before actually generating the gate clock signal. This pre-calculated reference time is then used for comparison to detect abnormalities, allowing the system to prevent display defects before they occur rather than reacting after abnormalities manifest.

The patent implements feedback by comparing the gate clock reference time with the gate clock actual time (obtained by feeding back the generated gate clock signal) and using the comparison result to control whether to invert the on-clock and off-clock signals. This closed-loop feedback mechanism automatically corrects abnormal gate clock signals by adjusting the clock inversion logic based on detected timing deviations.

The patent replaces complex mechanical or hardware-based clock signal monitoring mechanisms with a computational approach. The calculator computes the gate clock reference time based on software-defined parameters (on-clock signal period and number of gate clock signals), and the comparator performs digital timing comparison. This substitution of computational logic for physical monitoring mechanisms maintains timing precision while improving ease of operation.

The patent applies parameter changes by dynamically adjusting the inversion control of on-clock and off-clock signals based on the comparison result between reference time and actual time. When an abnormality is detected (timing deviation exceeds threshold), the system changes the operational parameters of the clock signal generation by inverting the clock signals, thereby correcting the timing precision without requiring manual intervention.

The patent applies the skipping principle by implementing a real-time automated correction mechanism that rapidly detects and corrects abnormal gate clock signals as they occur, rather than allowing defects to accumulate and requiring subsequent manual intervention. The comparator continuously monitors the gate clock actual time against the reference time and immediately triggers inversion control when abnormalities are detected, rushing through the correction process to prevent display quality defects before they affect productivity.

The patent implements self-service by designing an autonomous correction system where the calculator, comparator, and inversion control work together automatically without external intervention. The system self-detects timing abnormalities through feedback comparison and self-corrects by automatically inverting the on-clock and off-clock signals when needed, eliminating the need for manual debugging or production interruptions to address display quality defects.