Display Gate Driver Clock Wiring Asymmetry
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Solution Overview
Problem
Display apparatuses face issues with horizontal line smear due to ripple voltages generated in the reference voltage, which degrade display quality.
Innovation Solution
The arrangement of clock wirings and clock bar wirings in an alternate pattern reduces the difference in length between bridge wirings connected to these signals, thereby minimizing parasitic capacitances and the magnitude of ripple voltages, preventing horizontal line smear.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If clock wirings and clock bar wirings are arranged in a conventional manner, then the gate driver can be embedded in the display panel, but ripple voltage is generated in the reference voltage causing horizontal line smear
Solution Approach 1:
The patent applies asymmetry by arranging clock wirings and clock bar wirings in an alternating pattern rather than grouping them separately. This alternating arrangement creates asymmetric positioning that reduces the difference in length between bridge wirings connected to different clock signals, thereby minimizing parasitic capacitance differences and reducing ripple voltage in the reference voltage that causes horizontal line smear.
Solution Approach 2:
The patent changes the spatial arrangement parameter of the wirings from a conventional grouped layout to an alternating pattern. This parameter change in wiring arrangement directly affects the length difference of bridge wirings and the resulting parasitic capacitances, transforming the electrical characteristics to reduce ripple voltage magnitude and eliminate display artifacts.
2Ease of manufacture
If bridge wirings have different lengths due to conventional wiring arrangement, then wiring layout is simplified, but parasitic capacitance difference increases causing larger ripple voltage
Solution Approach 1:
The patent uses asymmetric alternating arrangement of clock and clock bar wirings to balance the lengths of bridge wirings. By positioning these wirings alternately, the path lengths from different clock signals to the gate driver stages become more equal, reducing parasitic capacitance differences and minimizing ripple voltage while maintaining manufacturability.
3Object-affected harmful factors
If clock wirings are arranged to minimize ripple voltage, then display quality improves, but wiring complexity increases
Solution Approach 1:
The patent segments the wiring arrangement into alternating units of clock wiring and clock bar wiring. This segmentation creates a repetitive alternating pattern that is systematically simple to implement despite the refined positioning requirements. The segmented approach makes the complex alternating arrangement manageable through regular repetition rather than irregular custom routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the occurrence of horizontal line smear, thereby enhancing display quality by minimizing ripple voltage magnitude.
Implementation Method 1
the difference decreases between the parasitic capacitances formed between the bridge wirings and the reference electrode
Data Source
AI summary
A display apparatus includes: a display panel includes: a plurality of pixels to display an image; a gate driver to drive the pixels; a first part electrically connected to the pixels; and a second part electrically connected to the gate driver. The gate driver includes: a plurality of stages to generate a gate signal to be provided to the pixels; k number of clock wirings to provide k number of clock signals to the plurality of stages; and k number of clock bar wirings to provide k number of clock bar signals to the plurality of stages (where k is a natural number of one or greater), and the second part includes: k number of clock pads electrically connected to the k number of clock wirings, respectively; and k number of clock bar pads electrically connected to the k number of clock bar wirings, respectively. The k number of clock wirings and the k number of clock bar wirings are arranged in a first order, and the k number of clock pads and the k number of clock bar pads are arranged in a second order different from the first order.