Display Gate Driver Circuit With Half-Cycle Signal Transfer
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Solution Overview
Problem
Display devices driven by an active matrix mode face issues with signal delay and distortion due to parasitic capacitance and resistance in gate lines, particularly as the pixel portion increases in quality, affecting image display.
Innovation Solution
The implementation of a display device with a first and second gate driver, each connected to odd-numbered and even-numbered gate lines respectively, utilizing flip-flop circuits and transfer signal generation circuits with specific input and output connections to reduce signal delay and distortion by introducing a half clock cycle delay, thereby improving signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pixel portion is made high-quality with increased definition and size, then the display quality is improved, but signal delay and distortion increase due to parasitic capacitance and resistance in gate lines
Solution Approach 1:
The gate driver is divided into multiple gate drivers (first gate driver and second gate driver) that are distributed across different sides of the pixel portion. Each gate driver independently controls specific gate lines, segmenting the signal transmission paths to reduce the impact of parasitic capacitance and resistance on any single path.
2Device complexity
If a single gate driver is provided close to one side of the pixel portion, then the device complexity is reduced, but the display portion becomes asymmetric and signal transmission issues arise
Solution Approach 1:
The patent deliberately introduces asymmetry by placing gate drivers on both sides of the pixel portion in a balanced configuration. This asymmetric placement relative to the pixel portion center actually achieves overall symmetry in the display device structure, improving both aesthetics and signal transmission balance.
Data Source
AI summary
It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.