Display Device Gate-Driver Layout for Seamless Tiled Screens
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Solution Overview
Problem
Existing display devices face challenges in increasing resolution without compromising the integration space for the gate driver and minimizing the non-display area between adjacent display devices, leading to a sense of disconnection.
Innovation Solution
The solution involves disposing a first stage of the gate driver on the left side of the clock line and a second stage on the right side between two adjacent unit pixel rows, ensuring the gate driver's freedom of arrangement and integrating space, while minimizing the non-display area by aligning pixel pitches across adjacent display devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If resolution is increased to improve display quality, then display precision is improved, but the integrated space for the gate driver is reduced
Solution Approach 1:
The gate driver is divided into first and second stages that are disposed on opposite sides of the clock signal line. This segmentation allows the gate driver to be distributed across the substrate rather than concentrated in one location, thereby maintaining sufficient integrated space even as resolution increases and pixel density becomes higher.
2Ease of manufacture
If non-display area between adjacent display devices is minimized to reduce sense of disconnection, then visual continuity is improved, but device complexity increases
Solution Approach 1:
The patent applies different pixel pitch designs to different regions: a first pixel pitch for display devices in a first region and a second pixel pitch for display devices in a second region. This local differentiation allows each region to be optimized independently, simplifying the overall design while achieving visual continuity at the boundaries where pixel pitches are matched.
Data Source
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AI summary
A display device including a substrate that includes a display area and a non-display area disposed at a side of the display area. The display area includes first through fourth areas. The fourth area includes a first sub-area adjacent to at least one of the first to third areas, and a second sub-area excluding the first sub-area. At least the second sub-area includes first pixels disposed in a first direction in a first pixel row, second pixels disposed in the first direction in a second pixel row that is a next row of the first pixel row, the second pixels spaced apart from the first pixels, a clock line extending in a second direction intersecting the first direction, and a gate driver including a first stage disposed left of the clock line in a plan view, and a second stage disposed right of the clock line in a plan view.