Display Gate Driver Timing for Consistent Pixel Charging
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Solution Overview
Problem
Conventional display technologies for high-definition displays, such as those used in VR, AR, and MR, face challenges in securing sufficient charging time for pixels due to increased circuit complexity and timing delays, which can lead to reduced image quality and uneven brightness across pixel rows.
Innovation Solution
A display device design featuring a gate driver with a shift register circuit and output circuits that generate logical products of register circuit outputs and enable signals, allowing for extended scanning signal durations and synchronized pixel signal application without additional circuitry, thereby maintaining consistent pixel charging across rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If vertical drive circuits are provided on both left and right sides of the pixel unit to delay writing time for pixels on the scanning end side, then the charging time of pixels is secured, but the circuit scale increases
Solution Approach 1:
The patent combines the vertical drive circuits into a single location (either left or right side) rather than providing circuits on both sides. The shifted clock signal mechanism allows the single drive circuit to control multiple scanning lines sequentially, achieving the same pixel charging function with reduced circuit scale.
Solution Approach 2:
The patent applies preliminary action by delaying the clock signal to the vertical drive circuit before it controls the scanning lines. This timing shift ensures that pixels on the scanning end side receive their charging signals at the appropriate time, securing sufficient charging time without requiring additional circuits.
2Duration of action of moving object
If a delay circuit and OR circuit are provided to each scanning signal line to secure charging time, then the charging time is extended, but the circuit complexity increases
Solution Approach 1:
The patent extracts the delay function from individual scanning signal lines and consolidates it into a single shifted clock signal that controls the vertical drive circuit. This eliminates the need for separate delay circuits and OR circuits on each scanning line, reducing overall circuit complexity while maintaining extended charging time.
Solution Approach 2:
The shifted clock signal serves multiple functions: it provides timing control for the vertical drive circuit, implements the delay function for scanning end side pixels, and synchronizes the operation across all scanning lines. This multi-functional approach replaces multiple specialized circuits with a single versatile timing mechanism.
3Duration of action of moving object
If the scanning signal duration is extended to secure pixel charging time, then the charging time is sufficient, but the image refresh rate decreases
Solution Approach 1:
The patent employs periodic action through the shifted clock signal that operates in synchronized cycles with the horizontal and vertical scanning. This periodic timing mechanism ensures that pixel charging occurs during appropriate time windows without extending the overall frame period, thereby maintaining the image refresh rate while providing sufficient charging time.
Solution Approach 2:
The patent implements dynamic timing control where the vertical drive circuit operates in synchronization with the horizontal scanning progress. The clock signal timing is dynamically adjusted based on the scanning line being activated, allowing optimal pixel charging duration without static extension of the entire scanning period, thus preserving refresh rate.
Data Source
AI summary
A display device includes a substrate having a display region in which a plurality of pixels are arrayed in a first direction and a second direction different from the first direction, a plurality of scanning lines coupled to the pixels arrayed in the first direction, a plurality of signal lines coupled to the pixels arrayed in the second direction, a gate driver configured to supply a scanning signal to the scanning lines, and a signal line selection circuit configured to supply a pixel signal to the signal lines.