Display Gate Driver Timing Overlap Reduces Line Memory
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Solution Overview
Problem
Display devices with UHD resolution face increased manufacturing costs due to the need for wider pulse widths of gate signals and the resulting increase in the number of line memories required, which complicates the timing control and increases power consumption.
Innovation Solution
A display device design that includes a timing controller generating a start signal within the vertical blank period, allowing for overlapping pulse widths of gate signals to adjacent gate lines while reducing the number of line memories needed by optimizing the timing of gate and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the pulse widths of gate signals are widened to allow sufficient charging time for UHD resolution, then the charging time is improved, but the number of line memories increases and manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by performing the gate signal pulse width extension during the vertical blank period, which is the time interval between frames when no active display is occurring. This allows the gate driver to supply wider pulse widths without extending the active display time, thereby providing sufficient charging time for UHD resolution while avoiding the need to increase the number of line memories.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the timing of gate signals to overlap with the vertical blank period. The gate driver is configured to supply gate signals whose pulse widths extend into the vertical blank period, creating a dynamic timing arrangement that accommodates longer charging requirements without requiring additional line memory resources.
2Duration of action of moving object
If the pulse widths of gate signals are widened to allow sufficient charging time for UHD resolution, then the charging time is improved, but the manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by performing the gate signal pulse width extension during the vertical blank period, which is the time interval between frames when no active display is occurring. This allows the gate driver to supply wider pulse widths without extending the active display time, thereby providing sufficient charging time for UHD resolution while avoiding the need to increase the number of line memories.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the timing of gate signals to overlap with the vertical blank period. The gate driver is configured to supply gate signals whose pulse widths extend into the vertical blank period, creating a dynamic timing arrangement that accommodates longer charging requirements without requiring additional line memory resources.
3Adaptability or versatility
If the number of line memories is increased to handle wider pulse widths, then the timing control capability is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent applies universality by making the vertical blank period serve multiple functions: it acts as both the transition interval between frames and the extended duration for gate signal pulse widths. This multi-functional use of the vertical blank period allows the existing line memories to handle wider pulse widths without requiring additional memory resources, thereby improving timing control capability while avoiding increased device complexity.
Solution Approach 2:
The patent applies preliminary action by performing the gate signal pulse width extension during the vertical blank period, which is the time interval between frames when no active display is occurring. This allows the gate driver to supply wider pulse widths without extending the active display time, thereby providing sufficient charging time for UHD resolution while avoiding the need to increase the number of line memories.
Data Source
AI summary
A display device is disclosed, which may supply gate signals to allow pulse widths of gate signals supplied to adjacent gate lines to be overlapped with each other and at the same time minimize cost increase caused by increase of the number of line memories. The display device comprises a display panel, a gate driver and a timing controller. The display panel includes gate lines, data lines and pixels provided at crossing areas between the gate lines and the data lines. The gate driver supplies gate signals to the gate lines. The timing controller supplies a start signal and gate clock signals for controlling an operation timing of the gate driver to the gate driver. One frame period includes an active period for supplying the gate signals to the gate lines and a vertical blank period for not supplying the gate signals to the gate lines, and the start signal is supplied within the vertical blank period.