Display Gate Driving Circuit Simplification Using Sequential Discharge
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of gate driving circuits in display devices leads to an enlarged bezel area, necessitating a simplification that maintains performance while reducing the design area.
Innovation Solution
A display device with a gate driving circuit that includes a power supply applying sequential discharge signals in a power off mode, utilizing transistors to manage gate and carry signals, and simplifying the discharge process by eliminating certain transistors and adding a third discharge signal, thereby reducing the bezel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate driving circuit is made more complex to improve performance, then the gate driving performance is enhanced, but the bezel area increases
Solution Approach 1:
The patent extracts and eliminates redundant discharge transistors (specifically removing three discharge transistors: one from the first stage, one from the second stage, and one from the output stage) while maintaining the essential discharge functionality through a simplified discharge signal application method, thereby reducing the circuit area in the bezel region
Solution Approach 2:
The simplified discharge circuit architecture allows the remaining transistors to perform multiple functions - the pull-down transistor handles both normal operation discharge and power-off discharge, while the Q node discharge transistor manages multiple stages' discharge needs, reducing the total transistor count while maintaining performance
2Area of stationary object
If the gate driving circuit is simplified to reduce bezel area, then the design area is reduced, but the gate driving performance may deteriorate
Solution Approach 1:
The patent applies discharge signals in a predetermined sequence (first discharge signal to the first stage, second discharge signal to the second stage, third discharge signal to the output stage) to ensure that all nodes are properly discharged before power-off, maintaining performance while using fewer transistors
Solution Approach 2:
The patent introduces a power supply unit that acts as an intermediary to apply discharge signals to the gate driving circuit nodes, enabling the simplified transistor configuration to achieve proper discharge functionality without compromising gate driving performance
Data Source
Figure 1
Figure 2~3
Figure 4~5
AI summary
A display device includes a display panel, a gate driving circuit having a plurality of stages, and a power supply for sequentially applying first to third discharge signals in a power off mode, wherein an n-th stage includes a pull-up transistor (Tup) that outputs a high-voltage gate signal in a driving mode, a pull-down transistor (Tdn) that outputs a low-voltage gate signal in the driving mode and discharges a gate signal output node in response to the second discharge signal in the power off mode, a Q node discharge transistor (T3) that charges and discharges the Q node and the QB node in the driving mode and discharges the Q node in response to the second discharge signal in the power off mode, and a QB node discharge transistor (T5q, Tst_qb) that discharges the QB node in response to the third discharge signal in the power off mode.