Display Gate Driving Layout for Shared Data Lines

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Solution Overview

Problem

Existing display devices using a double rate driving method face issues with insufficient gate signal supply to subpixels, particularly in configurations where two subpixels share a data line.

Innovation Solution

A display device design incorporating a first and second gate driving unit, controlled independently by a timing controlling unit, to consecutively supply gate signals to subpixels through separate gate lines, with shared data lines for subpixels of the same color, and a data driving unit to supply data signals based on luminance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If two subpixels commonly share one data line in a double rate driving method, then the number of data lines is reduced, but the gate signal is not sufficiently supplied to the subpixels

Engineering Contradiction:
Improvenumber of data linesVSAvoidgate signal supply sufficiency
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The gate driving unit is divided into multiple independent gate driving units (first gate driving unit, second gate driving unit, etc.), each responsible for driving specific gate lines. This segmentation allows each gate driving unit to independently supply gate signals without interference, ensuring sufficient gate signal supply even when data lines are shared between subpixels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a time dimension by consecutively supplying gate signals to different subpixels through different gate lines in sequence. The timing controlling unit coordinates the operation of multiple gate driving units to supply gate signals at different time points, effectively utilizing the time dimension to resolve the conflict between reduced data lines and sufficient gate signal supply.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple gate driving units are used to consecutively supply gate signals, then gate signal supply is improved, but the device complexity increases

Engineering Contradiction:
Improvegate signal supply sufficiencyVSAvoidgate driving unit configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple gate driving units are designed with identical or similar functional structures, each capable of performing the same gate signal generation and output function. This universality allows for standardized design and manufacturing processes, reducing the actual complexity despite the increased number of components. The timing controlling unit provides centralized coordination to manage the multiple gate driving units.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The timing controlling unit acts as an intermediary that coordinates the operation of multiple gate driving units. It generates timing control signals that synchronize the consecutive operation of different gate driving units, ensuring they work together harmoniously without direct complex interconnections between them, thereby managing system complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12380858B2Display device
Publication Date: 2025.08.05 LG DISPLAY CO LTD
  • US12380858B2 patent drawing
  • US12380858B2 patent drawing
  • US12380858B2 patent drawing

AI summary

A display device includes a display panel having a plurality of subpixels arranged in a row and a column; a first gate driving unit supplying a plurality of gate signals to the first subpixel through a plurality of first gate lines; a second gate driving unit supplying the plurality of gate signals to the second subpixel through a plurality of second gate lines; a data driving unit supplying a plurality of data signals through the plurality of data lines; and a timing controlling unit controlling the first gate driving unit, the second gate driving unit and the data driving unit, wherein the timing controlling unit controls the first gate driving unit independently from the second gate driving unit to consecutively supply the plurality of gate signals to the first subpixel through the plurality of first gate lines.