Display Panel Gate Drive Layout for Stable High-PPI Sub-Pixels
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Solution Overview
Problem
Current display technologies face challenges in efficiently driving sub-pixels due to instability in thin film transistors, affecting display quality, and require complex gate drive circuits that occupy significant space.
Innovation Solution
A display panel design with a gate drive circuit featuring cascaded shift registers and signal lines optimized for space efficiency, where input and reset signal lines are strategically arranged to reduce complexity and improve pixel drive circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex gate drive circuits are used to drive sub-pixels, then display quality can be maintained, but space occupancy increases and device complexity increases
Solution Approach 1:
The gate drive circuit is segmented into multiple shift registers arranged in a matrix configuration, where each shift register is responsible for driving a specific row or column of sub-pixels. This segmentation allows the overall gate drive function to be distributed across multiple simpler units rather than requiring a single complex circuit, thereby reducing device complexity while maintaining display quality.
Solution Approach 2:
The patent introduces a two-dimensional matrix arrangement of shift registers with cascade connections in both row and column directions. This dimensional transformation from traditional single-direction cascading to multi-directional matrix cascading enables more efficient space utilization and reduces the overall circuit complexity by distributing the driving function across multiple dimensions.
2Productivity
If traditional cascade connections are used for shift registers, then gate drive function is achieved, but space occupancy increases
Solution Approach 1:
The patent merges the cascade input signal lines and cascade display reset signal lines into shared communication paths within the matrix structure. By combining these signal transmission functions and utilizing common signal lines for multiple shift registers, the overall space occupancy is reduced while maintaining the necessary gate drive functionality.
Solution Approach 2:
The signal lines in the matrix structure are designed to serve multiple functions and multiple shift registers simultaneously. The cascade input signal lines and display reset signal lines are configured to be shared across different rows and columns, enabling universal usage of these signal paths and thereby reducing the total number of dedicated lines required, which directly reduces space occupancy.
3Productivity
If signal lines are densely arranged to increase pixels per inch, then display resolution improves, but signal line stability deteriorates
Solution Approach 1:
The signal transmission path is segmented into multiple independent cascade stages through the matrix arrangement of shift registers. By dividing the overall signal transmission into multiple smaller, manageable segments with intermediate buffering at each shift register stage, the patent reduces signal degradation and interference that would occur in densely packed configurations, thereby maintaining signal line stability while achieving high pixels per inch.
4Ease of manufacture
If gate drive circuit is integrated on the same side as sub-pixels, then manufacturing cost is reduced and yield improves, but space for sub-pixel arrangement is reduced
Solution Approach 1:
The gate drive circuit is arranged in a two-dimensional matrix structure on the same side as the sub-pixels, utilizing the available space in both horizontal and vertical dimensions. This multi-dimensional layout optimizes the use of the substrate area, allowing the gate drive circuit to be integrated without significantly reducing the space available for sub-pixel arrangement, thereby achieving both manufacturing efficiency and display area maximization.
Data Source
AI summary
A display panel includes: a substrate, sub-pixels and a gate drive circuit. The sub-pixel includes a pixel drive circuit. The gate drive circuit includes cascaded shift registers, and a shift register is electrically connected to pixel drive circuits in a row of sub-pixels. The gate drive circuit further includes cascade input signal lines and cascade display reset signal lines. The cascade input signal line is configured to connect a shift signal terminal and an input signal terminal of two different shift register, and the cascade display reset signal line is configured to connect a shift signal terminal and a display reset signal terminal of two different shift register. The display panel has sub-pixel regions for arranging the sub-pixels and first gap regions each located between two adjacent columns of sub pixel regions: the cascade display reset signal lines and the cascade input signal lines are disposed in different first gap regions.