Display Panel Gate Line Layout for Uniform Pixel Luminance
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Solution Overview
Problem
Current display devices face challenges in achieving improved display quality due to uneven load distribution and luminance differences between pixels driven by different gate drivers, leading to suboptimal display performance.
Innovation Solution
The display device incorporates a unique layout with alternating arrangements of auxiliary lines and gate lines, coupled with circuit films containing gate and data drivers, to ensure even load distribution and minimize luminance differences between adjacent pixels, thereby enhancing display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If pixels are driven by multiple gate drivers, then the display panel can be controlled, but uneven load distribution and luminance differences occur between pixels
Solution Approach 1:
The patent applies local quality by introducing auxiliary lines specifically in regions where load imbalance occurs (between pixels driven by different gate drivers). These auxiliary lines are selectively placed rather than uniformly distributed, providing localized compensation to achieve uniform luminance across the display panel while maintaining the multi-gate-driver control structure.
Solution Approach 2:
The patent changes the electrical parameters (voltage or current) applied to the auxiliary lines to compensate for load differences. By adjusting these parameters, the luminance of pixels experiencing higher or lower load can be balanced, thereby resolving the luminance uniformity issue while preserving the benefits of multiple gate drivers.
2Manufacturing precision
If auxiliary lines are added to balance load, then luminance uniformity improves, but device complexity increases
Solution Approach 1:
The patent segments the gate line structure by introducing auxiliary lines that are electrically connected to specific gate lines at specific locations. This segmentation allows the auxiliary lines to be independently controlled and connected only where needed, rather than creating a complex interconnected network across the entire display panel.
Solution Approach 2:
The auxiliary lines serve multiple functions: they compensate for load imbalance, improve luminance uniformity, and can be integrated with existing gate driver structures. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
3Manufacturing precision
If intermediate gate lines are placed between adjacent pixels, then load distribution is improved, but the number of gate lines increases
Solution Approach 1:
The patent employs asymmetric placement of intermediate gate lines and auxiliary lines, positioning them specifically between pixels driven by different gate drivers where load imbalance occurs. This asymmetric, targeted approach provides load distribution improvement without uniformly increasing the number of gate lines across the entire display panel.
Solution Approach 2:
The patent applies partial action by introducing intermediate gate lines and auxiliary lines only in specific regions where load balancing is needed, rather than adding them uniformly across all pixel regions. This selective placement achieves load distribution improvement with a minimal increase in the total number of gate lines.
Data Source
AI summary
A display device includes a display panel including pixels, data lines, first gate lines, auxiliary lines, and second gate lines electrically connected to the first gate lines, respectively, a first circuit film including a first gate driver and a first data driver, and a second circuit film spaced apart from the first circuit film and including a second gate driver and a second data driver. The first gate lines include first partial gate lines that receive a signal from the first gate driver, and second partial gate lines that receive a signal from the second gate driver. At least some of the auxiliary lines are disposed between the first partial gate lines and the second partial gate lines.