Display Panel Gate Drive Layout for Dense Sub-Pixel Routing
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Solution Overview
Problem
Current display technologies face challenges in efficiently driving sub-pixels due to instability in thin film transistors, affecting display quality, and require complex gate drive circuits that occupy significant space, limiting pixel density.
Innovation Solution
A display panel design with a gate drive circuit featuring cascaded shift registers and optimized signal line arrangements, where input and reset signal lines are grouped and positioned to reduce space usage and improve signal transmission efficiency, allowing for more compact and stable pixel drive circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate drive circuit is provided in the display panel to reduce costs and improve yield, then the manufacturing cost is reduced, but the signal transmission efficiency and reset operation complexity increase
Solution Approach 1:
The gate drive circuit is divided into multiple cascaded shift registers, where each shift register is divided into device groups located in different gap regions. This segmentation allows independent optimization of each module while maintaining overall functionality, reducing the complexity of the entire system.
Solution Approach 2:
The signal lines are routed through the gap regions between sub-pixel columns, utilizing the spatial dimension between functional elements. This three-dimensional arrangement of signal paths optimizes signal transmission efficiency while maintaining a compact two-dimensional layout on the display panel.
2Productivity
If the cascade input signal lines and cascade display reset signal lines are disposed in the first gap regions, then the signal transmission efficiency is improved, but the device layout complexity increases
Solution Approach 1:
Multiple signal lines (cascade input signal lines and cascade display reset signal lines) are merged and routed through the same gap regions between sub-pixel columns. This consolidation optimizes space utilization and improves signal transmission efficiency by reducing the number of separate routing paths required.
Solution Approach 2:
Different types of signal lines are assigned to different gap regions based on their functional requirements. The cascade input signal lines are disposed in one set of gap regions while cascade display reset signal lines are disposed in another set, allowing optimized local routing for each signal type.
3Reliability
If the shift register includes multiple device groups located in regions between adjacent sub-pixels, then the display performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The shift register is segmented into multiple device groups, with each group located in a specific gap region between adjacent sub-pixels. This segmentation isolates the precision requirements to smaller, more manageable units, making manufacturing more controllable while maintaining high display performance.
Solution Approach 2:
The gap regions between sub-pixels serve as intermediary spaces that host the device groups. These intermediary regions provide well-defined locations for placing transistors and capacitors, establishing clear reference points that simplify the manufacturing alignment process while ensuring optimal display performance.
Data Source
AI summary
A display panel includes: a substrate, sub-pixels and a gate drive circuit. The sub-pixel includes a pixel drive circuit. The gate drive circuit includes cascaded shift registers, and a shift register is electrically connected to pixel drive circuits in a row of sub-pixels. The gate drive circuit further includes cascade input signal lines and cascade display reset signal lines. The cascade input signal line is configured to connect a shift signal terminal and an input signal terminal of two different shift register; and the cascade display reset signal line is configured to connect a shift signal terminal and a display reset signal terminal of two different shift register. The display panel has sub-pixel regions for arranging the sub-pixels and first gap regions each located between two adjacent columns of sub-pixel regions; the cascade display reset signal lines and the cascade input signal lines are disposed in different first gap regions.