Display Gate Line Segmentation for Waveform Distortion
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Solution Overview
Problem
Liquid crystal display apparatuses face issues with waveform distortion in gate pulses due to impedance in gate wiring lines, leading to delayed pixel activation times and reduced image quality, especially with high frame rates and large pixel counts, as existing techniques fail to effectively address gate line delay and parasitic capacitance issues.
Innovation Solution
Incorporating waveform shaping circuits along the scanning lines to shape the scanning pulses, reducing impedance and capacitance effects, and optimizing the placement of power supply lines to minimize voltage drop and parasitic capacitance, thereby ensuring uniform signal propagation across the display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high frame rates and large pixel counts are implemented, then display performance and resolution are improved, but gate line delay and waveform distortion increase due to impedance and parasitic capacitance
Solution Approach 1:
The gate driving circuit is divided into multiple independent gate buffers distributed along the gate lines. Each gate buffer independently drives a segment of the gate lines, reducing the total impedance and parasitic capacitance effect on any single line. This segmentation allows high frame rates and large pixel counts to be achieved while maintaining waveform uniformity across the display.
2Area of stationary object
If gate wiring lines are extended to cover more pixels, then display area and resolution are improved, but impedance and parasitic capacitance increase causing delayed pixel activation
Solution Approach 1:
Instead of using a single long gate line driven from one end, the gate lines are segmented into multiple shorter segments, each driven by its own gate buffer. This reduces the effective length of any single driven line, thereby reducing impedance and parasitic capacitance effects, and ensuring uniform pixel activation timing across the entire display area.
Solution Approach 2:
Gate buffers are distributed not only along the horizontal gate lines but also arranged in multiple vertical columns. This two-dimensional distribution of driving points reduces the maximum distance any signal must travel, effectively reducing the impact of line impedance and capacitance on pixel activation timing.
3Device complexity
If conventional gate driving circuits are used, then device complexity is kept low, but waveform distortion and image quality deteriorate at high frame rates
Solution Approach 1:
The gate driving circuit is segmented into multiple identical gate buffer units distributed across the display. While this increases the total number of components, each individual buffer remains simple in design. This modular approach maintains manageable device complexity while significantly improving waveform uniformity and image quality at high frame rates.
Data Source
AI summary
Disclosed herein is a display apparatus, including, a pixel section, a plurality of scanning lines, a plurality of signal lines, and a driving circuit.