Display Substrate Gate-Line Layout to Prevent Dummy-Region Shorting
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Solution Overview
Problem
The accumulation of static electricity at the ends of active gate lines in a display substrate can lead to short-circuiting with dummy data lines, causing poor display quality due to the application of common voltage, especially when the gate insulating layer is broken down.
Innovation Solution
The design of the display substrate includes active gate lines with ends that do not overlap orthographically with dummy data lines, and dummy data lines are connected to a common voltage line without direct contact, ensuring a staggered arrangement to prevent short-circuiting and static electricity discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ends of active gate lines are extended into the dummy region to improve electrical connection, then the reliability of electrical connection is improved, but the risk of short-circuiting with dummy data lines increases due to overlapping projections
Solution Approach 1:
The patent resolves the contradiction by transitioning from a two-dimensional overlapping arrangement to a staggered spatial arrangement. The ends of active gate lines are positioned in the dummy region such that their orthographic projections do not overlap with dummy data lines, effectively using spatial dimensionality to avoid short-circuiting while maintaining electrical connection reliability.
Solution Approach 2:
The patent applies asymmetry by creating an uneven, staggered arrangement between active gate line ends and dummy data lines. Instead of symmetric overlapping, the design positions these elements asymmetrically in the dummy region, ensuring that projections do not coincide while maintaining necessary electrical connections.
2Ease of manufacture
If dummy data lines are placed in the dummy region to facilitate common voltage connection, then the ease of manufacture is improved, but the accumulation of static electricity at active gate line ends increases leading to potential damage
Solution Approach 1:
The patent introduces an intermediary spatial arrangement in the dummy region that mediates between the active gate lines and dummy data lines. By positioning elements such that their projections do not overlap, this intermediary arrangement prevents direct electrical contact that would allow static electricity discharge, while still facilitating common voltage connection through the dummy data lines.
Solution Approach 2:
The patent applies preliminary anti-action by pre-positioning the active gate line ends and dummy data lines in a staggered arrangement before any static electricity accumulation can occur. This preventive spatial configuration counteracts the potential harmful effect of static electricity discharge by eliminating the direct contact pathway in advance.
3Volume of moving object
If the gate insulating layer is made thinner to reduce overall device thickness, then the compactness is improved, but the susceptibility to breakdown and short-circuiting increases
Solution Approach 1:
The patent extracts the potential failure pathway by removing the overlapping projection relationship between active gate line ends and dummy data lines. By taking out this dangerous proximity in the spatial arrangement, the patent reduces the stress and breakdown risk on the gate insulating layer, allowing for thinner designs with maintained reliability.
Data Source
AI summary
A display substrate is provided to include a base substrate including an active display region and a dummy region, the dummy region includes at least one first dummy sub-region arranged in a first direction together with the active display region; active gate lines in the active display region and extending along the first direction, at least one end of at least one active gate line extends into a first dummy sub-region on the same side as the at least one end; and at least one dummy data line within the first dummy sub-region and extending along a second direction; an orthographic projection of an end of the at least one active gate line in the first dummy sub-region on the base substrate does not overlap with an orthographic projection of any dummy data line on the base substrate. A display panel and a display apparatus are further provided.