Display Module Gate-Line Switching for High-Frame Display and Detection
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Solution Overview
Problem
Existing display apparatuses face challenges in increasing frame frequency for display operations while maintaining high detection accuracy and reducing power consumption due to the need for separate control of light-emitting and light-receiving subpixels, which leads to increased circuit scale and power consumption.
Innovation Solution
A display apparatus with a novel structure that includes a timing control circuit to switch between operation modes, using a gate line driver circuit to output selection signals at different frame frequencies and periods for light-emitting and light-receiving subpixels, and integrates switching portions with analog switches to optimize signal allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If display operation and detection operation are alternately performed with different scan timings, then display quality is improved by increasing frame frequency, but circuit scale of driver circuits is increased
Solution Approach 1:
The patent combines the driver circuits for light-emitting subpixels and light-receiving subpixels into a unified driver circuit structure. The same driver circuit outputs selection signals to both types of subpixels by time-division multiplexing, where the driver circuit sequentially selects between display subpixels and detection subpixels within one frame period. This merging approach avoids duplicating driver circuits and reduces overall circuit scale while maintaining high frame frequency for display operations.
Solution Approach 2:
The patent implements dynamic switching of selection signal output timing within the driver circuit. The driver circuit dynamically adjusts its output timing to alternate between selecting light-emitting subpixels for display and light-receiving subpixels for detection. This dynamic time-division multiplexing allows the single driver circuit to serve dual purposes, reducing circuit complexity while enabling high frame frequency display operations.
2Measurement precision
If frequency of detection operation is increased to improve accuracy, then detection accuracy is improved, but power consumption is increased due to continual detection operations
Solution Approach 1:
The patent implements periodic detection operations within the frame period rather than continual detection. The light-receiving subpixels are selected and operated periodically at specific time intervals within each frame, alternating between display subpixel scanning and detection subpixel scanning. This periodic action allows the system to achieve necessary detection accuracy while minimizing power consumption by keeping detection operations dormant during periods when display operations are prioritized.
3Measurement precision
If number of selection signals to scan light-receiving subpixels is increased, then detection accuracy is improved, but power consumption is increased due to unnecessary detection operations
Solution Approach 1:
The patent applies partial action by selectively scanning only certain light-receiving subpixels rather than all subpixels continuously. Within the frame period, the driver circuit performs detection operations on a subset of light-receiving subpixels at specific time intervals, rather than continuously scanning all detection subpixels. This partial scanning approach achieves sufficient detection accuracy for biometric authentication while reducing power consumption by avoiding unnecessary detection operations on all subpixels at all times.
Data Source
AI summary
To provide a display apparatus with a novel structure. A display portion including a first subpixel, a second subpixel, a first gate line supplied with a first selection signal to scan the first subpixel, and a second gate line supplied with a second selection signal to scan the second subpixel; and a driver control circuit including a gate line driver circuit, a switching portion that allots the first selection signal or the second selection signal output from the gate line driver circuit to the first gate line or the second gate line to be output, and a timing control circuit that controls the switching portion are included. The timing control circuit allows the gate line driver circuit to output the first selection signal of a first frame frequency and the second selection signal having a selection period longer than the first selection signal in a first operation mode, and to output the first selection signal and the second selection signal with a second frame frequency lower than the first frame frequency in a second operation mode.