Display Gate Line Width Variation for Signal Delay Compensation
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Solution Overview
Problem
High-resolution display devices face image quality deterioration due to gate signal delays, which result in insufficient data signal charging during allocated one horizontal time, especially as resolution increases, leading to suboptimal operation.
Innovation Solution
A display device design incorporating a controller that delays data enable signals and image data by a desired gate delay time, ensuring data signals are output synchronously with gate signals, and adjusting gate line widths based on initial delay times to achieve optimal charging of pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the display device is increased, then the image quality should be improved, but the gate signal delay increases causing insufficient data signal charging in pixels
Solution Approach 1:
The gate lines are pre-designed with specific width variations along their length to compensate for signal delay before the actual display operation begins. This preliminary structural adjustment ensures that data signals arrive at pixels at the correct time despite the increased resolution causing longer gate line lengths and greater inherent delay.
Solution Approach 2:
Different sections of the gate lines have different widths to create localized delay compensation. The gate line width is adjusted at specific locations along its path to achieve the desired delay characteristics in different regions, allowing precise control over signal timing to match the increased resolution requirements.
2Speed
If the gate line width is increased to reduce delay, then the signal transmission speed improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of uniformly increasing gate line width throughout, the invention applies width variations only at specific locations where delay compensation is needed. This localized approach maintains signal transmission speed where required while avoiding unnecessary complexity in other regions of the gate line structure.
Solution Approach 2:
The gate line width parameter is strategically modified at specific positions rather than changing the entire gate line structure. This selective parameter adjustment achieves the desired signal speed improvement while minimizing the overall complexity increase and maintaining manufacturability.
3Ease of manufacture
If the gate line width is uniformly adjusted, then the manufacturing process is simplified, but the ability to precisely control delay time across different pixel rows deteriorates
Solution Approach 1:
The gate line structure incorporates localized width variations at specific positions along its length, allowing precise control over delay characteristics in different regions. This approach maintains manufacturing feasibility while achieving the required precision in delay time control for high-resolution displays.
Data Source
AI summary
A display device includes a display panel including a plurality of gate lines having a desired gate delay time, and a plurality of pixel rows, each of the plurality of pixel rows coupled to a corresponding one of the plurality of gate lines, a gate driver configured to sequentially provide a plurality of gate signals to the plurality of gate lines, a data driver configured to provide data signals to each of the plurality of pixel rows, and a controller configured to control the gate driver to sequentially output the plurality of gate signals and to control the data driver to output the data signals that are delayed by the desired gate delay time of the plurality of gate lines.