Display Pixel Gate Pattern for Reduced Circuit Area

The patent merges the function of multiple scan lines into a single scan line by using one scan line to sequentially supply scan signals to multiple transistors (T2, T3) across different rows. This is achieved by timing the turn-on of transistors so that the single scan line can deliver signals to Row 1, then Row 2, and subsequent rows in sequence, eliminating the need for separate scan lines for each row and reducing the overall pixel circuit area.

The patent implements periodic action by using a single scan line to repeatedly supply scan signals to different rows in a cyclic manner. The scan line alternates between supplying signals to transistors in Row 1, Row 2, and other rows at different time periods, ensuring that each row receives its required scan signals periodically without requiring dedicated scan lines for each row.

The patent merges multiple scan line functions into a single scan line that serves multiple rows. By using one scan line to sequentially address transistors in Row 1, Row 2, and subsequent rows, the design achieves high-resolution coverage without proportionally increasing the number of scan lines, thus preventing pixel circuit area expansion while maintaining display resolution.

The patent introduces a time dimension to the scan signal delivery process. Instead of providing simultaneous scan signals to multiple rows through multiple scan lines (spatial approach), the system delivers scan signals sequentially over time using a single scan line. This temporal multiplexing allows high-resolution coverage without increasing the spatial footprint of scan lines in the pixel circuit.