Display Device Gate Signal Phase Shifting to Reduce Feed-Through Voltage
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Solution Overview
Problem
Conventional display devices experience reduced display quality due to parasitic capacitance between gate lines, causing feed-through voltage issues during forward and reverse scans, which affects the optimal common voltage in pixel arrays.
Innovation Solution
A display device with a control circuit that provides phase-shifted start and stop signals to gate circuits for odd and even gate lines, ensuring that gate signals do not overlap during high voltage states, thereby minimizing secondary feed-through voltage by shifting the phases of the signals by at least one clock cycle during scanning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate circuits perform forward scan or reverse scan on pixel array, then the display device can scan the pixel array in multiple directions, but parasitic capacitance between gate lines causes different feed through voltage affecting optimal common voltage
Solution Approach 1:
The patent applies preliminary anti-action by introducing a compensation capacitor connected between the gate line and common voltage line. This capacitor is pre-configured to counteract the parasitic capacitance effect before it degrades the common voltage. During scanning operations, the compensation capacitor generates an opposing voltage effect that cancels out the feed-through voltage caused by parasitic capacitance, thereby maintaining consistent common voltage across different scan directions.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the compensation capacitance value based on scanning conditions. The compensation capacitor's effective capacitance is modified according to the scan direction (forward or reverse) and timing, allowing the system to optimize the compensation effect for each specific scanning scenario. This dynamic parameter adjustment ensures that the common voltage remains stable regardless of the scanning pattern used.
2Duration of action of moving object
If gate signal time width is greater than one gate line time width, then the gate circuit can provide sufficient signal duration, but feed through voltage is generated between adjacent gate lines
Solution Approach 1:
The patent applies the taking out principle by extracting and isolating the harmful feed-through voltage effect through the compensation capacitor. The compensation capacitor is specifically designed to capture and neutralize the feed-through voltage that appears on the common voltage line during gate signal transitions. By separating this harmful effect and applying targeted compensation, the system can maintain longer gate signal widths without suffering from adjacent line interference.
Solution Approach 2:
The compensation capacitor serves as an intermediary element between the gate line and common voltage line. It mediates the interaction between these two lines by providing a controlled capacitance path that counteracts the unwanted parasitic coupling. This intermediary component allows the gate signal to maintain its required duration while preventing the generation of harmful feed-through voltage on adjacent lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent feed-through voltage across gate lines, improving the quality of the display frame by preventing overlap of gate signals and reducing parasitic capacitance, thus enhancing the overall display performance.
Implementation Method 1
gate lines in a gate circuit are easily affected by parasitic effect to form parasitic capacitance, which causes feed through voltage to be generated between each of the gate lines
Data Source
AI summary
A display device and driving method thereof are provided. In the display device, a control circuit provides first and second start signals. In a display panel, a pixel array has a plurality of odd and even gate lines. A first and second gate circuits respectively receive the first and second start signals, and respectively provide the sequentially enabled first and second gate signals to odd and even gate lines according to the phases of the first and second start signals, respectively. One of the first and second start signals is phase-shifted by at least one clock cycle from a preset phase during a first scan period that scans from a first side to a second side of the pixel array or during a second scan period that scans from the second side to the first side of the pixel array.