Display Device Gate Signal Overlap Control

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Solution Overview

Problem

Display devices suffer from motion blur and excessive brightness issues, particularly in OLED displays, due to uneven voltage charge ratios across subpixels, leading to unclear object boundaries and overly bright lines during image display.

Innovation Solution

The implementation of a display device with a data driving circuit and gate driving circuit that supply image or fake data to subpixels, utilizing a level shifter to modulate clock signals and adjust gate signal periods, ensuring overlap and non-overlap periods for improved voltage charge ratios and reduced motion blur.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If gate signals are supplied with equal magnitude throughout the turn-on level period, then the circuit design is simple, but specific lines become excessively bright causing non-uniform image quality

Engineering Contradiction:
Improvecircuit design simplicityVSAvoidimage quality uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by dividing the gate signal turn-on level period into two distinct periods: an overlap period where the gate signal has a first magnitude, and a non-overlap period where the gate signal has a second magnitude. This allows different regions of the signal waveform to have different characteristics, preventing excessive brightness in specific lines while maintaining overall image quality uniformity.

Inventive Principle:
Principle #3Local quality

2Reliability

If the turn-on level period of gate signals is extended to improve voltage charge ratios, then subpixel charging is improved, but motion blur increases due to longer charging time

Engineering Contradiction:
Improvevoltage charge ratioVSAvoidmotion blur
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the parameter of gate signal magnitude over time within the turn-on level period. By transitioning from a first magnitude during the overlap period to a second magnitude during the non-overlap period, the patent optimizes the voltage charge ratio while controlling the total charging time to minimize motion blur effects.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If data writing is performed continuously without interruption, then productivity is high, but voltage charge ratios become uneven across subpixels

Engineering Contradiction:
Improvedata writing efficiencyVSAvoidvoltage charge ratio uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent implements preliminary action by supplying fake data to the data lines before the gate signal for the (n+1)th gate line is supplied. This preliminary data supply ensures that data writing is prepared in advance, allowing the subsequent gate signal to charge subpixels uniformly without interrupting the overall data writing flow, thus maintaining both productivity and voltage charge ratio uniformity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11100870B2Display device
Publication Date: 2021.08.24 LG DISPLAY CO LTD
  • US11100870B2 patent drawing
  • US11100870B2 patent drawing
  • US11100870B2 patent drawing

AI summary

A display device may include: a display panel including a plurality of sub pixels; a data driving circuit configured to supply image data or fake data to a plurality of data lines; and a gate driving circuit configured to supply gate signals to a plurality of gate lines. The data driving circuit may supply the fake data to the plurality of data lines before the gate signal for an (n+1)th gate line is supplied after the gate signal for an n-th gate line is supplied, and a turn-on level period of the gate signal for the n-th gate line may include an overlap period that overlaps a turn-on level period of the gate signal for an (n−1)th gate line and a non-overlap period that does not overlap the turn-on level period of the gate signal for the (n−1)th gate line.