Display Substrate Gate Timing Layout for Residual Image Reduction
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Solution Overview
Problem
Existing display technologies using electroluminescent diodes suffer from residual image issues due to differences in bias effects causing non-uniform display brightness, which are not effectively addressed by current methods.
Innovation Solution
A display substrate design with a driver block containing a first gate drive circuit and pixel unit groups, where the first gate line is connected to a specific first signal output terminal and the reset signal line is connected to another terminal, allowing for extended duration of reset voltage application on the driving transistor, combined with a second gate drive circuit and light emission control circuit to improve uniformity of driving current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the reset voltage duration is extended to reduce bias effect differences, then the uniformity of display brightness is improved, but the device complexity increases due to additional gate drive circuits and signal output terminals
Solution Approach 1:
The pixel units are divided into n pixel unit groups, with each group having dedicated first and second gate lines and reset signal lines. This segmentation allows independent control of reset voltage duration for different pixel groups, enabling extended reset duration for specific groups to compensate for bias effects while maintaining overall system manageability through modular organization
Solution Approach 2:
The patent implements dynamic control of reset voltage duration by configuring different pixel unit groups with varying reset signal timings. The first gate drive circuit outputs reset signals at different time points for different pixel unit groups, allowing the reset voltage duration to be dynamically adjusted based on the specific bias effect requirements of each group, thereby improving brightness uniformity
Solution Approach 3:
The first gate drive circuit is designed with multi-functionality, serving both as a gate drive circuit for the first gate lines and as a reset signal output circuit for the reset signal lines. The n+x first signal output terminals can sequentially output both gate drive signals and reset signals, reducing the need for separate dedicated reset signal generators and thereby managing device complexity
2Manufacturing precision
If multiple first signal output terminals are used to control different pixel unit groups, then the uniformity of driving current is improved, but the device complexity increases due to additional circuits and terminals
Solution Approach 1:
The pixel units are divided into n pixel unit groups, with each group having dedicated first gate lines and reset signal lines. This segmentation allows independent control of driving signals for different pixel groups, enabling precise adjustment of driving current uniformity while managing complexity through modular organization of n+x signal output terminals
Solution Approach 2:
The first gate drive circuit is designed with multi-functionality, serving both as a gate drive circuit for the first gate lines and as a reset signal output circuit for the reset signal lines. The n+x first signal output terminals can sequentially output both gate drive signals and reset signals, reducing the need for separate dedicated reset signal generators and thereby managing device complexity
Data Source
AI summary
The embodiments of the present disclosure provides a display substrate, including: an active region and a peripheral region, the active region is provided therein with a plurality of pixel units arranged in an array, all the pixel units are divided into n pixel unit groups, the peripheral region is provided therein with a driver block including a first gate drive circuit having n+x first signal output terminals configured to sequentially output first gate drive signals in an active level and the first gate line provided for an ith pixel unit group is electrically connected to a (i+x)th first signal output terminal, and the reset signal line provided for the ith pixel unit group is electrically connected to an ith first signal output terminal, with i being a positive integer and i≤n.