Display Pixel Gate Timing for Lower Variable-Frequency Power

The patent segments the gate signal frequencies into different groups: data writing gate signals operate at one frequency while data initialization and compensation gate signals operate at different frequencies. This segmentation allows independent optimization of each signal type's frequency, reducing overall power consumption by avoiding unnecessary high-frequency operation of all gate signals simultaneously.

The patent changes the frequency parameter of gate signals dynamically based on driving conditions. In variable frequency driving, it sets the frequency of data initialization and compensation gate signals to be different from (specifically lower than) the frequency of data writing gate signals, thereby optimizing power consumption through parameter adjustment without compromising display performance.

The patent implements dynamic frequency adjustment where the frequency of data writing gate signals can be independently optimized based on driving conditions. By allowing variable frequency operation specifically for data writing signals while maintaining different frequencies for initialization and compensation signals, the system achieves dynamic balance between power consumption and data writing speed.

The patent employs periodic gate signals with different frequencies for different functions. Data writing, initialization, and compensation operations use periodic signals at different frequency rates, allowing the system to optimize power consumption by reducing the frequency of non-critical operations (initialization and compensation) while maintaining adequate frequency for critical data writing operations.