Display Gate Driving Circuit With Intermediate Voltage Control
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Solution Overview
Problem
Existing display apparatuses face challenges in stably outputting gate signals due to inefficiencies in gate driving circuits, leading to potential fluctuations and increased power consumption.
Innovation Solution
A driving circuit design incorporating a plurality of stages with specific transistor configurations and voltage levels, including N-channel and P-channel transistors, capacitors, and phase-shifted clock signals, to stabilize output signals and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate driving circuits are used, then the display apparatus can operate, but the gate signals are unstable and power consumption is high
Solution Approach 1:
The patent changes the voltage level parameters of the gate driving circuit by introducing a third voltage level (ELVDD/2) in addition to the traditional high voltage (ELVDD) and low voltage (ELVSS) levels. This parameter change enables more precise control of the transistor switching states, resulting in stable gate signal output while reducing power consumption through optimized voltage transitions.
Solution Approach 2:
The patent implements dynamic control of the gate driving circuit by using clock signals to periodically switch between different voltage levels. The control circuit dynamically adjusts the voltage levels at various nodes based on the clock signal phases, enabling stable signal propagation while minimizing power consumption through controlled switching operations.
2Reliability
If conventional gate driving circuits are used, then the circuit structure is simple, but the gate signal output is unstable
Solution Approach 1:
The patent segments the gate driving circuit into multiple independent stages, where each stage includes specific transistor configurations (first transistor T11, second transistor T12, third transistor T13) and control circuits. This segmentation allows each stage to independently generate stable gate signals through controlled voltage transitions, improving overall reliability while maintaining a modular structure that is manageable in complexity.
Solution Approach 2:
The patent introduces intermediate control circuits that mediate between the input signals and the output gate signals. These control circuits use clock signals and intermediate voltage levels (ELVDD/2) to precisely control the switching states of transistors, ensuring stable signal propagation through the circuit while adding only necessary control functionality.
3Loss of energy
If voltage levels are not properly managed, then the circuit operation is simple, but power consumption increases and signal stability decreases
Solution Approach 1:
The patent systematically manages voltage levels by defining specific voltage parameters (ELVDD, ELVSS, ELVDD/2) and controlling their application to different nodes at different times. The control circuit switches between these voltage levels based on clock signal phases, optimizing power consumption by minimizing unnecessary voltage transitions while ensuring stable signal levels throughout the circuit.
Solution Approach 2:
The patent employs periodic clock signals to control the voltage level transitions in the gate driving circuit. The clock signals periodically switch the transistors between on and off states, creating a rhythmic pattern of voltage transitions that reduces power consumption by avoiding continuous switching while maintaining stable signal output through controlled periodic operation.
Data Source
AI summary
A driving circuit includes: an output circuit connected between a first terminal and a second terminal, and for outputting an output signal of a first voltage level or a second voltage level according to voltage levels of a first node and a second node, and a control circuit connected to the output circuit and an input terminal, and for controlling the voltage levels of the first node and the second node. The control circuit includes: a first transistor connected between the input terminal and a third node; a second transistor connected between the third node and a fourth node; a third transistor connected between the fourth node and the first node; and an inverter connected between the first terminal and the second terminal and for controlling a voltage of the second node to a voltage level obtained by inverting the voltage level of the first node.