Display Gate Driver Voltage Segmentation for Crosstalk Reduction
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Solution Overview
Problem
Liquid crystal display (LCD) apparatuses face issues with vertical crosstalk and faded colors due to the off-voltage level of gate signals applied to gate electrodes of thin film transistors, which affect display quality.
Innovation Solution
A display apparatus and method that involve generating a series of gate-off voltages with progressively negative levels over time, along with temperature-compensated voltages, to optimize the gate signal for the thin film transistors, reducing vertical crosstalk and increasing the faded color margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed gate-off voltage level is applied to the gate line, then the device complexity is low, but vertical crosstalk and faded color occur reducing display quality
Solution Approach 1:
The gate-off voltage is segmented into multiple levels (first gate-off voltage and second gate-off voltage) applied at different time periods. During an initial period, a first gate-off voltage level is applied, and after a threshold time elapses, a second gate-off voltage level is applied. This temporal segmentation resolves the contradiction by improving display quality through multiple voltage levels while keeping the generation mechanism relatively simple through time-based switching.
Solution Approach 2:
The gate-off voltage level is made dynamic rather than fixed. The system automatically transitions from a first gate-off voltage level to a second gate-off voltage level based on elapsed time from power-on. This dynamic adjustment improves display quality by adapting to transistor characteristic changes over time, while the automation reduces operational complexity.
2Reliability
If the gate-off voltage level is adjusted over time, then vertical crosstalk and faded color are reduced, but the device complexity increases
Solution Approach 1:
The system performs preliminary action by establishing a threshold time value in advance that represents the optimal transition point for gate-off voltage levels. This pre-determined threshold simplifies the timing control logic, as the controller only needs to compare elapsed time against this preset value rather than implementing complex real-time analysis, thus reducing timing control complexity while maintaining display quality improvements.
Solution Approach 2:
The system implements feedback through the timing controller that monitors elapsed time from power-on and automatically switches gate-off voltage levels based on this time information. This closed-loop time-based feedback mechanism improves display quality by ensuring optimal voltage levels are applied at appropriate times, while the feedback logic remains simple through direct time comparison against a threshold.
Data Source
AI summary
A display apparatus includes a display panel comprising a plurality of pixels, each of the pixels comprising a thin film transistor connected to a gate line and a data line and a display element connected to the thin film transistor, a driving voltage generator configured to generate a gate-on voltage and a plurality of gate-off voltages, a timing controller configured to divide an initial driving period into a plurality of setting periods and output a gate-off voltage corresponding to each of the setting periods, and a gate driver circuit configured to generate a gate signal using the gate-on voltage and the gate-off voltage corresponding to a setting period and output the gate signal to the gate line.