Active Matrix Display Gray Level Control via Power Drive Signal Timing
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Solution Overview
Problem
In active matrix image display devices using organic EL elements, sharing pixel circuit control among multiple scan lines leads to increased coupling capacitance between signal and scan lines, making it difficult to set the gray level properly for pixel circuits due to changes in signal line potential.
Innovation Solution
The image display device includes pixel circuits with a light-emitting element, drive transistor, and holding capacitor, where the write transistor controls the terminal voltage of the holding capacitor to alternate between light emission and non-light emission periods, and the power drive signal is pulled up at times other than when the write signal connects the holding capacitor to the signal line, allowing for proper gray level setting even with shared scan line control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pixel circuit control using scan lines is shared among a plurality of lines, then the scan line drive circuit configuration is simplified, but the coupling capacitance between signal lines and scan lines increases, making it impossible to set the gray level properly
Solution Approach 1:
The power drive signal is pulled up to high level in advance (before the write signal goes high) to prepare the signal line potential. This preliminary action ensures that when the write transistor connects the holding capacitor to the signal line, the signal line is already at the correct potential, preventing gray level setting errors even when scan lines are shared among multiple lines
Solution Approach 2:
The power drive signal is controlled to change periodically - pulled up before the write signal and pulled down after the write signal. This periodic timing control ensures proper gray level setting during each writing cycle while maintaining the benefit of shared scan lines
Data Source
AI summary
Disclosed herein is an image display device including a display section formed by arranging pixel circuits in a matrix form. Each pixel circuit includes at least a light emitting element, a drive transistor, a holding capacitor, and a write transistor. A light emission and non-light emission periods are alternately repeated. A light emission period start voltage and a non-light emission period start voltage are alternately output to the signal line. The terminal voltage of the holding capacitor is set to start the light emission and non-light emission periods. The write signal is set to sequentially delay the timings. The power drive signal is set in units of a plurality of successive lines. The drain voltage of the drive transistor is pulled up to high level at a time other than when the one of the terminals is connected to the signal line by the write signal in different lines.