Display Device Holding Capacitor Insulating Layer Thickness
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Solution Overview
Problem
In display devices with interconnected upper electrodes, the thin insulating layer between the upper and lower electrodes can lead to electrical short circuits due to disconnection or thinness near the outer peripheral ends, resulting in low manufacturing yield.
Innovation Solution
The upper electrode is formed in an island shape with its outer peripheral end overlapping the lower electrode, and a first connection wiring line connects adjacent pixel circuits, ensuring the insulating layer thickness is maintained to prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the insulating layer is made thin to increase capacitance, then the holding capacitor capacitance increases, but electrical short circuits occur between upper and lower electrodes
Solution Approach 1:
The patent applies different insulating layer thicknesses at different locations: a first insulating layer with thickness T1 is formed in the region where the upper electrode overlaps the lower electrode, while a second insulating layer with greater thickness T2 is formed in the connection wiring line region. This local differentiation allows sufficient capacitance where needed while preventing short circuits in connection regions, directly resolving the contradiction between capacitance enhancement and short circuit prevention.
2Ease of manufacture
If upper electrodes are connected to form power source lines, then power source potential supply is improved, but manufacturing yield decreases due to short circuits
Solution Approach 1:
The patent implements local quality differentiation by forming a thicker second insulating layer (thickness T2) specifically in the connection wiring line regions where upper electrodes are connected, while maintaining a thinner first insulating layer (thickness T1) in the capacitor overlap regions. This localized approach enables reliable power source potential supply through connected upper electrodes while preventing manufacturing yield loss from short circuits in connection areas.
3Quantity of substance
If the insulating layer thickness is reduced to increase capacitance, then holding capacitor performance improves, but the insulating layer becomes disconnected at outer peripheral ends
Solution Approach 1:
The patent applies local quality by forming a first insulating layer with thickness T1 in the capacitor overlap region to maximize capacitance, and a second insulating layer with greater thickness T2 in the connection wiring line region to ensure continuity and prevent disconnection at outer peripheral ends. This spatially differentiated insulating layer structure simultaneously achieves high capacitance and maintains insulating layer stability.
4Measurement precision
If higher definition is achieved through smaller pixel circuits, then display resolution improves, but holding capacitor area and capacitance decrease
Solution Approach 1:
The patent changes the insulating layer thickness parameter differentially across different regions: a thinner first insulating layer (thickness T1) is used in the capacitor overlap region to maximize capacitance density, while a thicker second insulating layer (thickness T2) is used in connection regions for reliability. This parameter differentiation enables sufficient capacitance in smaller pixel circuits for high-definition displays without compromising reliability.
Data Source
AI summary
(i) A holding capacitor formed of a second electrode serving as an upper electrode, a first electrode serving as a lower electrode, a second passivation film sandwiched between the second electrode and the first electrode, and an upper gate insulating film, (ii) a drive transistor including a gate electrode connected to the holding capacitor are included, and a plurality of pixel circuits arranged in a matrix, and a first connection wiring line electrically connecting the first electrodes of two pixel circuits adjacent to each other in a row direction are included, the second electrode being formed in an island shape, and the entirety of an outer peripheral end of the second electrode overlapping the first electrode in a plan view.


