Display Driver IC SRAM Layout With Shared Bus Lines
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Solution Overview
Problem
The challenge is to optimize the wiring structure of a display driver integrated circuit (DDIC) to accommodate a static random-access memory (SRAM) with a large capacity in a limited space, as the physical size of SRAM limits its placement area.
Innovation Solution
The DDIC is designed with a static random-access memory divided into multiple memory areas, each containing at least two memory blocks, and connected to a bus through non-repeating transmission lines. Each transmission line serves multiple memory blocks, and a switch module controls data transmission based on the need for image data output, optimizing the wiring structure to reduce line count and allocate more space for SRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity of static random-access memory is increased, then the image data storage capability is improved, but the physical area occupied by the memory increases, reducing the available placement area in the display driver integrated circuit
Solution Approach 1:
The patent divides the static random-access memory into multiple memory areas, with each area containing multiple memory blocks. This segmentation allows the memory to be organized in a way that optimizes both capacity and area utilization. By dividing the large-capacity memory into smaller functional units, the design achieves high storage capacity while maintaining efficient space distribution across the integrated circuit placement area.
2Speed
If each memory block is connected to its own dedicated transmission line, then the data transmission speed is improved, but the number of transmission lines increases, complicating the wiring structure and consuming more placement area
Solution Approach 1:
The patent implements a multi-functional transmission line architecture where each transmission line can serve multiple memory blocks across different memory areas. The transmission lines are designed to dynamically select and connect to different memory blocks based on data transmission needs. This universal approach allows a reduced number of transmission lines to handle the data traffic that would otherwise require dedicated lines for each memory block, thereby simplifying the wiring structure while maintaining efficient data transmission capabilities.
3Productivity
If more transmission lines are used to connect memory blocks to the bus, then the image data output capability is improved, but the placement area available for memory is reduced
Solution Approach 1:
The patent employs a dynamic transmission line allocation system where the connection between transmission lines and memory blocks is not fixed but can be dynamically configured based on the current data output requirements. The system can activate only the necessary transmission lines at any given moment, allowing memory blocks to be selectively connected to the bus. This dynamic approach enables high image data output capability while minimizing the actual area occupied by active transmission pathways, thereby preserving more placement area for memory expansion.
Data Source
AI summary
The present application discloses a display driver integrated circuit and a control method thereof, relating to the technical field of display. An object of the present application mainly lies in that the display driver integrated circuit includes: a bus, a static random-access memory divided into a plurality of memory areas, and a plurality of transmission lines connected to the bus; wherein each of the memory areas includes at least two memory blocks; each of the transmission lines is respectively connected to a plurality of memory blocks in a corresponding manner, and the memory blocks connected to each of the transmission lines are not repeated.