Display Base Layer Inner Hole Layout for Pixel Light Isolation

The patent introduces a line-free area that segments the base layer into distinct regions: a pixel circuit formation area where pixel circuits are located, and a line-free area where lower lines are absent. This spatial segmentation prevents light interference by ensuring that light emitting elements positioned in the line-free area do not interfere with pixel circuit components in the pixel circuit formation area, while still maintaining high area utilization through efficient spatial arrangement.

The patent applies local quality by creating a line-free area with specific properties (absence of lower lines) in a localized region of the base layer, while other regions maintain their standard structure with lower lines. This allows the light emitting elements in the line-free area to be free from light interference, while the rest of the device maintains manufacturing simplicity through the presence of lower lines in other areas.

The patent resolves the alignment precision issue by transitioning to a three-dimensional arrangement where the line-free area is defined in the planar dimension, allowing light emitting elements to be positioned above this area at a different vertical level. This dimensional separation enables compact device size while maintaining sufficient alignment tolerance, as the light emitting elements are vertically positioned over the line-free area rather than requiring precise lateral alignment with pixel circuit components.