Display Data Interface Bit Ordering to Reduce EMI and Power
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Solution Overview
Problem
The increasing transfer amount of digital image data in display apparatuses with larger screen resolutions leads to higher electromagnetic interference (EMI) and power consumption due to the increased number of transitions between '0' and '1' in data transfer.
Innovation Solution
A data interface device and method that encodes and decodes image data using a pixel clock to arrange bits of different colors in a specific order within data transfer packets, reducing the number of transitions and minimizing EMI and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If image data is transferred with conventional bit arrangement, then data transfer completeness is ensured, but the number of transitions between '0' and '1' increases, leading to increased EMI and power consumption
Solution Approach 1:
The patent applies asymmetry by arranging bits of different colors (first color and second color) in opposite orders within the data transfer packet. Specifically, the most significant bit of the first color data is positioned closer to the first delimiter, while the most significant bit of the second color data is positioned closer to the second delimiter. This asymmetric arrangement reduces the number of transitions between '0' and '1' during data transfer, thereby decreasing electromagnetic interference and power consumption while maintaining data integrity.
2Use of energy by stationary object
If image data is transferred with conventional bit arrangement, then data transfer completeness is ensured, but power consumption increases due to repeated voltage level switching
Solution Approach 1:
The patent applies asymmetry by arranging bits of different colors (first color and second color) in opposite orders within the data transfer packet. Specifically, the most significant bit of the first color data is positioned closer to the first delimiter, while the most significant bit of the second color data is positioned closer to the second delimiter. This asymmetric arrangement reduces the number of transitions between '0' and '1' during data transfer, thereby decreasing electromagnetic interference and power consumption while maintaining data integrity.
Data Source
AI summary
A device for controlling a data interface of a display apparatus, can include a timing controller to encode one data transfer packet including image data according to a pixel clock to output the one data transfer packet to an interface line, and a source driver to decode the one data transfer packet to recover the image data. Also, the image data includes first image data of a first color and second image data of a second color between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value, a most significant bit of the first image data is closer to the first delimiter signal than a least significant bit of the first image data, and a most significant bit of the second image data is closer to the second delimiter signal than a least significant bit of the second image.